jtd.drc
来自「交通灯控制,在A和B方向各用数码管显示剩余的时间.」· DRC 代码 · 共 5 行
DRC
5 行
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net SF668 is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.DRC detected 0 errors and 1 warnings.
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