代码搜索：pha
找到约 824 项符合「pha」的源代码
代码结果 824
www.eeworm.com/read/385756/6307893
v top.v
//`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:09:21 08/29/2006
// Design Name:
// Mod
www.eeworm.com/read/229301/14346281
v sinewave.v
module top(clkin,
rst,
// B,
NCS0_n,
NWE_n,
addr,
DataIN,
SINE1,
SINE2,
SINE3,
SINE4,
SINE5,
SINE6,
clk
www.eeworm.com/read/248485/12557095
m low_mul_quan.m
function Bq=Low_Mul_quan(a,Bi,Fs,Pha_Sub,Ds,f,i)
% Low_Mul_quan.m 量化a1和Bi
% $date 11/10/2005
%
% 作者：赵泽平
% vf1983cs@163.com
%
%
% References:
% Miroslav D. Lutovac, Dejan
www.eeworm.com/read/308751/13693431
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity dds4 is
port(
data_fre1 : in vl_logic_vector(15 downto 0);
data_fre2 : in vl_logic_vector(15 downto 0);
www.eeworm.com/read/308751/13693483
ant dds_tbw.ant
// D:\商共享资料\程序\两路正弦波
// Verilog Annotation Test Bench created by
// HDL Bencher 6.1i
// Tue Apr 22 16:57:52 2008
`timescale 1ns/1ns
`define C_NOP 7
`define C_READ 5
`define IF2 3
`define s
www.eeworm.com/read/308751/13693556
v dds1.v
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08:51:50 04/04/2007
// Design Name:
// Modul
www.eeworm.com/read/385579/8798377
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