top.v

FPGA程序的top.v文件

//`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    09:09:21 08/29/2006 
// Design Name: 
// Module Name:    top 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////



module top(clkin,
			  rst,
			  
			 // B,
			 			 
           NCS0_n,
			  NWE_n,
			  addr,
			  DataIN,
						  
			  SINE1,
			  SINE2,
			  SINE3,
			  SINE4,
			  SINE5,
			  SINE6,
			  SINE7,
			  SINE8,
			  clk_out
			  		  
          	);

input clkin;              //50M clock;
input rst;


//input B;
//input CE;      
//input SCLR;					  //asynchronism clear

//input MCK;            //
input NCS0_n;
input NWE_n;            //
input [4:0] addr;
input [15:0] DataIN;
   
                    
output [7:0]SINE1; 		  //output sin wave
output [7:0]SINE2;
output [7:0]SINE3;
output [7:0]SINE4;
output [7:0]SINE5;
output [7:0]SINE6;
output [7:0]SINE7;
output [7:0]SINE8;
output clk_out;             //D/A clk


reg [15:0] DATA_FRE1,DATA_PHA1,PHA_ACC1;
reg [15:0] DATA_FRE2,DATA_PHA2,PHA_ACC2;
reg [15:0] DATA_FRE3,DATA_PHA3,PHA_ACC3;
reg [15:0] DATA_FRE4,DATA_PHA4,PHA_ACC4;
reg [15:0] DATA_FRE5,DATA_PHA5,PHA_ACC5;
reg [15:0] DATA_FRE6,DATA_PHA6,PHA_ACC6;

reg [7:0]SINE2;
reg [7:0]SINE4;
reg [7:0]SINE6;
reg [7:0]SINE8;
wire CLK0;


//wire CLK180t;
wire CLKDV_OUT;




my_dcm1 instance_name (
    .LOCKED_OUT(), 
    .CLKIN_IN(clkin), 
    .CLK180_OUT(), 
    .CLKFX_OUT(CLKDV_OUT), 
    .CLK0_OUT(CLK0), 
    .CLKIN_IBUFG_OUT()
    );




reg [15:0] CONTROL;
reg [2:0] num;
//reg [3:0] num;
//reg [7:0] SINE;
//reg [15:0] data;

parameter wordwidth_data=16,memsize_data=32;
reg [wordwidth_data-1:0] ram_data [memsize_data-1:0];



wire [27:0] clkdata0;
wire clk_x0;
assign clkdata0 = 28'd200000000;

counter counterclk(rst,CLK0,clk_x0,clkdata0);
always @(posedge CLK0)
	begin
		SINE2<=8'b11111111;
		SINE4<=8'b11111111;
//		SINE6<=8'b11111111;
//		SINE8<=8'b11111111;
	end

/*
always @(posedge clk_x0 or negedge clk_x0)
   begin
		if(clk_x0)
		 SINE2<=8'b10000000;
		else
		 SINE2<=8'b11111111;
   end	 

 
always @(posedge clk_x0 or posedge rst)
   begin
		 if(rst)
			 begin
				 SINE6<=8'b00010000;
				 num<=4'b0000;
			 end
		 else
			 begin
				if(num==0)
					begin
					SINE6<=8'b00010000;
					num<=num+4'b0001;
   				end
				else
				   begin
					SINE6<=SINE6+8'b00010000;
					num<=num+4'b0001;
					end
				end	
   end

always @(posedge clk_x0 or posedge rst)
   begin
		 if(rst)
			 begin
				 SINE8<=8'b00010000;
				 num<=4'b0000;
			 end
		 else
			 begin
				if(num==0)
					begin
					SINE8<=8'b00010000;
					num<=num+4'b0001;
   				end
				else
				   begin
					SINE8<=SINE8+8'b00010000;
					num<=num+4'b0001;
					end
				end	
   end
*/	

always @(posedge clk_x0 or posedge rst)
   begin
		 if(rst)
			 begin
				 SINE6<=8'b00100000;
				 num<=3'b000;
			 end
		 else
			 begin
				if(num==0)
					begin
					num<=num+3'b001;
					SINE6<=8'b00100000;
					
   				end
				else
				   begin
					SINE6<=SINE6+8'b00001000;
					num<=num+3'b001;
					end
				end	
   end

always @(posedge clk_x0 or posedge rst)
   begin
		 if(rst)
			 begin
				 
				 SINE8<=8'b00100000;
				 num<=3'b000;
			 end
		 else
			 begin
				if(num==0)
					begin
					num<=num+3'b001;
					SINE8<=8'b00100000;
					
   				end
				else
				   begin
					SINE8<=SINE8+8'b00100000;
					num<=num+3'b001;
					end
				end	
   end

always @(posedge NWE_n  or posedge rst)

if(rst)
begin
ram_data[0]<=16'b0000001111110000;//sclr+we

//ram_data[1]<=16'b0000100011110111;
ram_data[1]<=16'b0000000001000001;
ram_data[2]<=16'b0000100011110111;		  //频率控制字
ram_data[3]<=16'b0000001010001111;
ram_data[4]<=16'b0000100011110111;
ram_data[5]<=16'b0000100011110111;
ram_data[6]<=16'b0000100011110111;

ram_data[7]<=0;
ram_data[8]<=0;										//相位控制字
ram_data[9]<=0;
ram_data[10]<=0;
ram_data[11]<=16'b1000000000000000;
ram_data[12]<=0;

//ram_data[13]<=16'b0000011111111111;
ram_data[13]<=16'b0000011111111111;
ram_data[14]<=0;								//相位步长控制字
ram_data[15]<=0;
ram_data[16]<=0;
ram_data[17]<=0;
ram_data[18]<=0;

ram_data[19]<=0;
ram_data[20]<=0;
ram_data[21]<=0;
ram_data[22]<=0;
ram_data[23]<=0;
ram_data[24]<=0;


ram_data[25]<=0;
ram_data[26]<=0;
ram_data[27]<=0;
ram_data[28]<=0;
ram_data[29]<=0;
ram_data[30]<=0;
ram_data[31]<=0;
end
else if(NCS0_n==0)
      begin
		//ram_data[1]<=16'b0000010011110111;
      ram_data[addr]<=DataIN;
      end
     else
      ram_data[addr]<=ram_data[addr];
    

always @ (posedge CLK0 or posedge rst)

if(rst)
begin
CONTROL<=0;
DATA_FRE1<=0;
DATA_FRE2<=0;
DATA_FRE3<=0;
DATA_FRE4<=0;
DATA_FRE5<=0;
DATA_FRE6<=0;
DATA_PHA1<=0;
DATA_PHA2<=0;
DATA_PHA3<=0;
DATA_PHA4<=0;
DATA_PHA5<=0;
DATA_PHA6<=0;
end
//else if(NCS0_n==1)
else
begin
 CONTROL<=ram_data[0];
 
 DATA_FRE1<=ram_data[1];
 //DATA_FRE1<=16'b0000010011110111;
 DATA_FRE2<=ram_data[2];
 DATA_FRE3<=ram_data[3];
 DATA_FRE4<=ram_data[4];
 DATA_FRE5<=ram_data[5];
 DATA_FRE6<=ram_data[6];
 
 DATA_PHA1<=ram_data[7];
 DATA_PHA2<=ram_data[8];
 DATA_PHA3<=ram_data[9];
 DATA_PHA4<=ram_data[10];
 DATA_PHA5<=ram_data[11];
 DATA_PHA6<=ram_data[12];
 
 PHA_ACC1<=ram_data[13];
 PHA_ACC2<=ram_data[14];
 PHA_ACC3<=ram_data[15];
 PHA_ACC4<=ram_data[16];
 PHA_ACC5<=ram_data[17];
 PHA_ACC6<=ram_data[18];
 
end 

dds4 my_dds4(
    .DATA_FRE1(DATA_FRE1), 
    .DATA_FRE2(DATA_FRE2), 
    .DATA_FRE3(DATA_FRE3), 
    .DATA_FRE4(DATA_FRE4),
    .DATA_FRE5(DATA_FRE5), 
    .DATA_FRE6(DATA_FRE6),
    	 
    .DATA_PHA1(DATA_PHA1), 
    .DATA_PHA2(DATA_PHA2), 
    .DATA_PHA3(DATA_PHA3), 
    .DATA_PHA4(DATA_PHA4),
    .DATA_PHA5(DATA_PHA5), 
    .DATA_PHA6(DATA_PHA6),
	 
	 .PHA_ACC1(PHA_ACC1),
	 .PHA_ACC2(PHA_ACC2),
	 .PHA_ACC3(PHA_ACC3),
	 .PHA_ACC4(PHA_ACC4),
	 .PHA_ACC5(PHA_ACC5),
	 .PHA_ACC6(PHA_ACC6),
	 
    .CONTROL(CONTROL), 
    //.BUTTON(B), 
    .RST(rst), 
    .CLK0(CLKDV_OUT), 
	 
    .SINE1(SINE1), 
    .SINE2(SINE3), 
    .SINE3(SINE5), 
    .SINE4(SINE7)
//	 .SINE5(SINE5), 
//  .SINE6(SINE6)
    );



assign clk_out=~CLKDV_OUT;

/*
always @(posedge clk_x0)
begin	
	SINE<=data[7:0];
end
*/
endmodule