_primary.vhd

Verilog编程

library verilog;
use verilog.vl_types.all;
entity dds4 is
    port(
        data_fre1       : in     vl_logic_vector(15 downto 0);
        data_fre2       : in     vl_logic_vector(15 downto 0);
        data_fre3       : in     vl_logic_vector(15 downto 0);
        data_fre4       : in     vl_logic_vector(15 downto 0);
        data_fre5       : in     vl_logic_vector(15 downto 0);
        data_fre6       : in     vl_logic_vector(15 downto 0);
        data_pha1       : in     vl_logic_vector(15 downto 0);
        data_pha2       : in     vl_logic_vector(15 downto 0);
        data_pha3       : in     vl_logic_vector(15 downto 0);
        data_pha4       : in     vl_logic_vector(15 downto 0);
        data_pha5       : in     vl_logic_vector(15 downto 0);
        data_pha6       : in     vl_logic_vector(15 downto 0);
        pha_acc1        : in     vl_logic_vector(15 downto 0);
        pha_acc2        : in     vl_logic_vector(15 downto 0);
        pha_acc3        : in     vl_logic_vector(15 downto 0);
        pha_acc4        : in     vl_logic_vector(15 downto 0);
        pha_acc5        : in     vl_logic_vector(15 downto 0);
        pha_acc6        : in     vl_logic_vector(15 downto 0);
        control         : in     vl_logic_vector(15 downto 0);
        rst             : in     vl_logic;
        clk0            : in     vl_logic;
        sine1           : out    vl_logic_vector(7 downto 0);
        sine2           : out    vl_logic_vector(7 downto 0);
        sine3           : out    vl_logic_vector(7 downto 0);
        sine4           : out    vl_logic_vector(7 downto 0);
        sine5           : out    vl_logic_vector(7 downto 0);
        sine6           : out    vl_logic_vector(7 downto 0)
    );
end dds4;