dds1.v

Verilog编程

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    08:51:50 04/04/2007 
// Design Name: 
// Module Name:    DDS1 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module DDS1(
   DATA_FRE,
	DATA_PHA,
	PHA_ACC,
   WE,
   CLK,
   SCLR,
	rst,
	
   SINE
   ); 
   input [15 : 0] DATA_FRE,DATA_PHA,PHA_ACC;
   input WE;
   input CLK;
   input SCLR;
	input rst;
	
   output [10 : 0] SINE;
reg [1:0]flag;	
reg [15 : 0] acc;
reg [15 : 0] acc_t;
reg [15 : 0] DATA_FRE_t;				 //允许频率改变控制字
reg [15 : 0] DATA_PHA_t;			    //允许相位改变控制字
reg [15 : 0] PHA_ACC_t;              //允许相位步长改变控制字
reg [15 : 0] PHA_ACC_t1;			    //相位累加

wire[9:0]SINE_T;
//reg [25:0] count;
	
always @ (posedge CLK or posedge rst)

if(rst)
begin
acc<=0;
acc_t<=0;
DATA_FRE_t<=0;
DATA_PHA_t<=0;
PHA_ACC_t<=0;
flag<=0;

end
else
begin
if(WE)
begin
DATA_FRE_t<=DATA_FRE;
DATA_PHA_t<=DATA_PHA;
PHA_ACC_t<=PHA_ACC;
end
else
begin
DATA_FRE_t<=DATA_FRE_t;
DATA_PHA_t<=DATA_PHA_t;
end
acc_t<=acc_t+DATA_FRE_t;
acc<=acc_t+DATA_PHA_t+PHA_ACC_t1;   //

if(acc[15]==0)
	begin
flag<=2;
end
else
	begin
flag<=0;
end
end
wire [25:0] clkdata;
wire clk_x;
assign clkdata = 26'd50000000;

counter counterclk(rst,CLK,clk_x,clkdata);	//	分频

always @ (posedge clk_x or posedge rst)

if(rst)
PHA_ACC_t1<=0;
else
PHA_ACC_t1<=PHA_ACC_t1+PHA_ACC_t;


	rom1 rom(
	.addr(acc[15:5]),
	.clk(CLK),
	.dout(SINE_T),
	.en(~SCLR)
	);
 assign SINE=SINE_T*(flag-1)+11'b10000000000;
endmodule