代码搜索:modelSim
找到约 1,834 项符合「modelSim」的源代码
代码结果 1,834
www.eeworm.com/read/405978/11452019
sft freq2_2.sft
set tool_name "ModelSim (Verilog)"
set corner_file_list {
{{"Slow Model"} {freq2_2.vo freq2_2_v.sdo}}
}
www.eeworm.com/read/130423/14194874
mti keyscanprj.cr.mti
D:/Modeltech_5.7d/YYH_ModelSim_Examples/keyscan/keyscan_test.v {1 {vlog -work work D:/Modeltech_5.7d/YYH_ModelSim_Examples/keyscan/keyscan_test.v
Model Technology ModelSim SE vlog 5.7d Compiler 2003.
www.eeworm.com/read/127506/14351342
transcript
# Reading e:/modelsim/tcl/vsim/pref.tcl
# do fen_fen_test_v_tf.fdo
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim XE II vlog 5.7c Compiler 2003.03 Mar 15 20
www.eeworm.com/read/412328/11204464
mti divclk2proj.cr.mti
G:/debug/modelsim/DivClk2HDL.vhd {1 {vcom -work work -2002 -explicit -vopt G:/debug/modelsim/DivClk2HDL.vhd
Model Technology ModelSim SE vcom 6.2b Compiler 2006.07 Jul 31 2006
-- Loading package sta
www.eeworm.com/read/235010/14089050
gfl ise_test.gfl
# XST (Creating Lso File) :
ddr_command.lso
# xst flow : RunXST
ddr_command.syr
ddr_command.prj
ddr_command.sprj
ddr_command.ana
ddr_command.stx
ddr_command.cmd_log
ddr_command.ngc
ddr_comm
www.eeworm.com/read/290161/8501010
prj vr_fifo.prj
#
##-- Synplicity, Inc.
##-- Project file vr_fifo.prj.
##-- Generated using ISE.
#implementation: vr_fifo
impl -add "vr_fifo"
##device options
proc findmatch {spec args} { set _Arglist [jo
www.eeworm.com/read/431824/8651735
vstf vish_stacktrace.vstf
# Current time Wed Jan 30 21:15:39 2008
# ModelSim Stack Trace
# Program = vish
# Id = "6.0"
# Version = "2004.08"
# Date = "Aug 19 2004"
# Platform = win32
Exception c0000005 has occurred at
www.eeworm.com/read/179424/9357497
env syndos.env
ABEL5DEV=d:\isptools\ispcpld\lib5
DIOEDA_ABEL5DEV=d:\isptools\ispcpld\lib5
DIOEDA_AppNotes=d:\isptools\ispcpld\bin
DIOEDA_Bin=d:\isptools\ispcpld\bin
DIOEDA_Config=d:\isptools\ispcpld\config
DIOE
www.eeworm.com/read/271056/11010419
cmp sisr_tb.cmp
; -- modelsim script - can be adapted for other simulators
; --
vcom -work DFT $misr_vhdl/ml_lfsr.vhd
vcom -work DFT $misr_vhdl/sig_reg.vhd
vcom -work DFT $misr_vhdl/sisr.vhd
vcom -work DFT $m
www.eeworm.com/read/462922/7191605
do sim.do
#退出上一次仿真
quit -sim
#建立work库
vlib work
#把ModelSim所要使用的work库映射到新建立的work库上
vmap work work
#编译Altera的仿真库文件
vlog altera_mf.v
#编译设计文件
vlog DualPortRAM.v
#编译顶层文件
vlog TOP.v
#编译testben