ise_test.gfl

一个小测试程序希望,朋友有所帮助,赶快下吧@@!!VERILOG

# XST (Creating Lso File) : 
ddr_command.lso
# xst flow : RunXST
ddr_command.syr
ddr_command.prj
ddr_command.sprj
ddr_command.ana
ddr_command.stx
ddr_command.cmd_log
ddr_command.ngc
ddr_command.ngr
# ProjNav -> New Source -> TBW
d:\verilog\ise_test\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
test_ddr_command.vhw
test_ddr_command.ano
test_ddr_command.tfw
# ModelSim : Simulate Behavioral Verilog Model
test_ddr_command.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# View RTL Schematic
ddr_command.ngr
# ModelSim : Simulate Behavioral Verilog Model
test_ddr_command.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral Verilog Model
test_ddr_command.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
ddr_command.lso
# xst flow : RunXST
ddr_command.syr
ddr_command.prj
ddr_command.sprj
ddr_command.ana
ddr_command.stx
ddr_command.cmd_log
ddr_command.ngc
ddr_command.ngr
# ModelSim : Simulate Behavioral Verilog Model
test_ddr_command.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
f:\ise_test/_ngo
ddr_command.ngd
ddr_command_ngdbuild.nav
ddr_command.bld
.untf
ddr_command.cmd_log
# Implementation : Map
ddr_command_map.ncd
ddr_command.ngm
ddr_command.pcf
ddr_command.nc1
ddr_command.mrp
ddr_command_map.mrp
ddr_command.mdf
__projnav/map.log
ddr_command.cmd_log
MAP_NO_GUIDE_FILE_CPF "ddr_command"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
ddr_command.twr
ddr_command.twx
ddr_command.tsi
ddr_command.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
ddr_command.ncd
ddr_command.par
ddr_command.pad
ddr_command_pad.txt
ddr_command_pad.csv
ddr_command.pad_txt
ddr_command.dly
reportgen.log
ddr_command.xpi
ddr_command.grf
ddr_command.itr
ddr_command_last_par.ncd
__projnav/par.log
ddr_command.placed_ncd_tracker
ddr_command.routed_ncd_tracker
ddr_command.cmd_log
PAR_NO_GUIDE_FILE_CPF "ddr_command"
# Implementation : Generate Post-Par Simulation Model
ddr_command_timesim.v
ddr_command_timesim.sdf
ddr_command_timesim.sdf
ddr_command_timesim.v
ddr_command_timesim.nlf
ddr_command.par_nlf
ddr_command.versim_par
ddr_command.cmd_log
__projnav/netgen_par_tcl.rsp
# Simulation :Simulate Post-Place & Route Verilog Model
test_ddr_command.timesim_tfw
_remap.tmp
__projnav/temp.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
test_ddr_command.tdo
# ModelSim : Simulate Post-Place & Route Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Implementation : Generate Post-Translate Simulation Model
ddr_command_translate.v
ddr_command_translate.v
ddr_command_translate.nlf
ddr_command.xlate_nlf
ddr_command.versim_xlate
ddr_command.cmd_log
# Simulation :Simulate Post-Translate Verilog Model
test_ddr_command.translate_tfw
_remap.tmp
__projnav/temp.rsp
# ModelSim : Simulate Post-Translate VHDL Model
test_ddr_command.ndo
# ModelSim : Simulate Post-Translate Verilog Model
vsim.wlf