vr_fifo.prj

可预取的fifo 的fpga 设计代码

#
##-- Synplicity, Inc.
##-- Project file vr_fifo.prj.
##-- Generated using ISE.

#implementation: vr_fifo
impl -add "vr_fifo"

##device options
proc findmatch {spec args} {  set _Arglist [join $args " "];  set _Idx [lsearch -glob $_Arglist $spec];  if {$_Idx != -1} {  return [lindex $_Arglist $_Idx];  } else {  return $spec;  }  }
         
proc findpackage {spec} { findmatch $spec [partdata -package [part]]}
proc findgrade   {spec} { findmatch $spec [partdata -grade   [part]]}
set_option -technology SPARTAN3E
set_option -part xc3s500e
set_option -package [findpackage {ft256}]
set_option -speed_grade [findgrade {-4}]

## Libraries

## Source files
add_file -verilog {"D:/synplicity/fpga_81/bin/../lib/xilinx/unisim.v"}
add_file {E:/modelsim/vr_fifo/src/vr_fifo_rtl.vhd}

## Additional _Compile options
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1
set_option -default_enum_encoding default
set_option -top_module vr_fifo
set_option -use_fsm_explorer 0

## Additional _Map options
set_option -frequency 0
set_option -fanout_limit 100
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -modular 0
set_option -retiming 0

## Additional _Simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

## Additional _PlaceAndRoute options
set_option -write_apr_constraint 1

## Additional _ImplAttr options
set_option -num_critical_paths 0
set_option -num_startend_points 0

set_option -vlog_std v2001
set_option -compiler_compatible 0

##--Set result format/file last
project -result_file {E:/modelsim/vr_fifo/par/vr_fifo.edn}

##-- p_Constraint file
add_file -constraint {E:/modelsim/vr_fifo/par/vr_fifo.sdc}