vr_fifo.bld

来自「可预取的fifo 的fpga 设计代码」· BLD 代码 · 共 26 行

Release 8.1.03i ngdbuild I.27
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc vr_fifo.ucf -p
xc3s500e-ft256-4 vr_fifo.edn vr_fifo.ngd 

Executing edif2ngd -quiet "vr_fifo.edn" "_ngo\vr_fifo.ngo"
Release 8.1.03i - edif2ngd I.27
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
Reading NGO file 'E:/modelsim/vr_fifo/par/_ngo/vr_fifo.ngo' ...

Applying constraints in "vr_fifo.ucf" to the design...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 66968 kilobytes

Writing NGD file "vr_fifo.ngd" ...

Writing NGDBUILD log file "vr_fifo.bld"...