代码搜索：modelSim

找到约 1,834 项符合「modelSim」的源代码

代码结果 1,834
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/316255/3612456

xrf colorbar_modelsim.xrf

vendor_name = ModelSim source_file = 1, E:/code/EP1C6/S6_VGA/src/vga_vl.v source_file = 1, E:/code/EP1C6/S6_VGA/Src/ColorBar.bdf source_file = 1, D:/RedLogic/RMC_samples_EP1C20/S5_VGA/Proj/stp1.stp
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www.eeworm.com/read/301574/3837629

lib modelsim_work.lib

[PRIM_DFFE] A/PRIM_DFFE=22|d:/quartus/bin/../eda/sim_lib/stratix_atoms.v|31|1*897165 B/PRIM_DFFE=3*1744683 R=d:/quartus/bin/../eda/sim_lib/stratix_atoms.v|31 [and1] A/and1=22|d:/quartus/bin/../
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www.eeworm.com/read/299888/3849694

sav modelsim.ini.sav

[Library] others = $MODEL_TECH/../modelsim.ini fusion = $MODEL_TECH/../actel/vlog/fusion presynth = presynth postsynth = postsynth postlayout = ../designer/impl1/simulation/postlayout
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www.eeworm.com/read/285694/4047535

lib modelsim_work.lib

[PRIM_DFFE] A/PRIM_DFFE=22|d:/quartus/bin/../eda/sim_lib/stratix_atoms.v|31|1*897165 B/PRIM_DFFE=3*1744683 R=d:/quartus/bin/../eda/sim_lib/stratix_atoms.v|31 [and1] A/and1=22|d:/quartus/bin/../
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www.eeworm.com/read/270378/4239662

xrf uart_if_modelsim.xrf

vendor_name = ModelSim source_file = 1, D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/UART/sythesis/uart_if.vqm source_file = 1, D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/UART/src/div1_8m.
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www.eeworm.com/read/442519/1759604

xrf fpmul_modelsim.xrf

vendor_name = ModelSim source_file = 1, E:/VHDL programs/FPmul/Fpmul.vhd source_file = 1, E:/VHDL programs/SAmul1/SAMul1.vhd source_file = 1, E:/VHDL programs/FPmul/Round/Round.vhd source_file = 1
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www.eeworm.com/read/442519/1759608

xrf round_modelsim.xrf

vendor_name = ModelSim source_file = 1, E:/VHDL programs/FPmul/Round/Round.vhd source_file = 1, E:/VHDL programs/FPmul/Round/Round.vwf design_name = Round instance = comp, \en~I\, en, Round, 1 in
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www.eeworm.com/read/437570/1830576

xrf traffic_modelsim.xrf

vendor_name = ModelSim source_file = 1, E:/实验/单片机/kechengsheji/traffic/traffic.vhd source_file = 1, E:/实验/单片机/kechengsheji/traffic/traffic.vwf source_file = 1, E:/实验/单片机/kechengsheji/traffic/testbe
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www.eeworm.com/read/427629/1969378

v sram_modelsim.v

`timescale 1ns / 1ps module sram_test(clk, rst, data1, addr1, ce1, we1, oe1, data2, addr2, ce2, we2
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www.eeworm.com/read/423643/2025180

xrf ffti_modelsim.xrf

vendor_name = ModelSim source_file = 1, I:/fftinterface/ff.vhd source_file = 1, I:/fftinterface/ramdata.vhd source_file = 1, I:/fftinterface/ramwave.vhd source_file = 1, I:/fftinterface/TRANS.vhd
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