uart_if_modelsim.xrf

this is a sample about UART transmission,it s default installation is D:RedLogicRCII_samples, and th

vendor_name = ModelSim
source_file = 1, D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/UART/sythesis/uart_if.vqm
source_file = 1, D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/UART/src/div1_8m.v
source_file = 1, D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/UART/physical/uart_if_rom.bdf
source_file = 1, D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/UART/physical/uart_rom.mif
source_file = 1, D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/UART/Src/filter.v
source_file = 1, D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/UART/physical/uart_rom.v
source_file = 1, c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf
source_file = 1, c:/altera/quartus50/libraries/megafunctions/stratix_ram_block.inc
source_file = 1, c:/altera/quartus50/libraries/megafunctions/lpm_mux.inc
source_file = 1, c:/altera/quartus50/libraries/megafunctions/lpm_decode.inc
source_file = 1, c:/altera/quartus50/libraries/megafunctions/aglobal50.inc
source_file = 1, c:/altera/quartus50/libraries/megafunctions/altsyncram.inc
source_file = 1, c:/altera/quartus50/libraries/megafunctions/a_rdenreg.inc
source_file = 1, c:/altera/quartus50/libraries/megafunctions/altrom.inc
source_file = 1, c:/altera/quartus50/libraries/megafunctions/altram.inc
source_file = 1, c:/altera/quartus50/libraries/megafunctions/altdpram.inc
source_file = 1, c:/altera/quartus50/libraries/megafunctions/altqpram.inc
source_file = 1, c:/altera/quartus50/libraries/megafunctions/cbx.lst
source_file = 1, D:/RedLogic_2_1/RCA-CY1C12/RedLogic/RCII_samples/UART/physical/db/altsyncram_g5q.tdf
design_name = uart_if_rom
instance = comp, \inst5|acc[12]~I , inst5|acc[12], uart_if_rom, 1
instance = comp, \inst2|cnt[15]~I , inst2|cnt[15], uart_if_rom, 1
instance = comp, \inst5|acc[11]~I , inst5|acc[11], uart_if_rom, 1
instance = comp, \inst2|cnt[14]~I , inst2|cnt[14], uart_if_rom, 1
instance = comp, \inst5|acc[10]~I , inst5|acc[10], uart_if_rom, 1
instance = comp, \inst2|cnt[13]~I , inst2|cnt[13], uart_if_rom, 1
instance = comp, \inst5|acc[9]~I , inst5|acc[9], uart_if_rom, 1
instance = comp, \inst|cnt_3_ , inst|cnt_3_, uart_if_rom, 1
instance = comp, \inst2|cnt[12]~I , inst2|cnt[12], uart_if_rom, 1
instance = comp, \inst5|acc[8]~I , inst5|acc[8], uart_if_rom, 1
instance = comp, \inst|cnt_0_ , inst|cnt_0_, uart_if_rom, 1
instance = comp, \inst|cnt_1_ , inst|cnt_1_, uart_if_rom, 1
instance = comp, \inst|cnt_2_ , inst|cnt_2_, uart_if_rom, 1
instance = comp, \inst2|cnt[11]~I , inst2|cnt[11], uart_if_rom, 1
instance = comp, \inst5|acc[7]~I , inst5|acc[7], uart_if_rom, 1
instance = comp, \inst|U1|u1|clkdiv_3_ , inst|U1|u1|clkdiv_3_, uart_if_rom, 1
instance = comp, \inst2|cnt[10]~I , inst2|cnt[10], uart_if_rom, 1
instance = comp, \inst5|acc[6]~I , inst5|acc[6], uart_if_rom, 1
instance = comp, \inst|U1|u1|clkdiv_2_ , inst|U1|u1|clkdiv_2_, uart_if_rom, 1
instance = comp, \inst|U1|u1|clkdiv_1_ , inst|U1|u1|clkdiv_1_, uart_if_rom, 1
instance = comp, \inst|U1|u1|clkdiv_5_sum3_a_Z , inst|U1|u1|clkdiv_5_sum3_a_Z, uart_if_rom, 1
instance = comp, \inst2|cnt[9]~I , inst2|cnt[9], uart_if_rom, 1
instance = comp, \inst5|acc[5]~I , inst5|acc[5], uart_if_rom, 1
instance = comp, \inst|U1|u1|clk1x_enable_Z , inst|U1|u1|clk1x_enable_Z, uart_if_rom, 1
instance = comp, \inst|U1|u1|clkdiv_0_ , inst|U1|u1|clkdiv_0_, uart_if_rom, 1
instance = comp, \inst2|cnt[8]~I , inst2|cnt[8], uart_if_rom, 1
instance = comp, \inst5|acc[4]~I , inst5|acc[4], uart_if_rom, 1
instance = comp, \inst2|cnt[7]~I , inst2|cnt[7], uart_if_rom, 1
instance = comp, \inst5|acc[3]~I , inst5|acc[3], uart_if_rom, 1
instance = comp, \inst2|cnt[6]~I , inst2|cnt[6], uart_if_rom, 1
instance = comp, \inst5|acc[2]~I , inst5|acc[2], uart_if_rom, 1
instance = comp, \inst2|cnt[5]~I , inst2|cnt[5], uart_if_rom, 1
instance = comp, \inst5|acc[1]~I , inst5|acc[1], uart_if_rom, 1
instance = comp, \inst2|cnt[4]~I , inst2|cnt[4], uart_if_rom, 1
instance = comp, \inst5|acc[0]~I , inst5|acc[0], uart_if_rom, 1
instance = comp, \inst2|cnt[3]~I , inst2|cnt[3], uart_if_rom, 1
instance = comp, \inst2|cnt[2]~I , inst2|cnt[2], uart_if_rom, 1
instance = comp, \inst2|cnt[1]~I , inst2|cnt[1], uart_if_rom, 1
instance = comp, \inst2|cnt[0]~I , inst2|cnt[0], uart_if_rom, 1
instance = comp, \rst_n~I , rst_n, uart_if_rom, 1
instance = comp, \inst2|rst_out~I , inst2|rst_out, uart_if_rom, 1
instance = comp, \inst|U1|u2|no_bits_sent_0_ , inst|U1|u2|no_bits_sent_0_, uart_if_rom, 1
instance = comp, \inst|U1|u2|no_bits_sent_1_ , inst|U1|u2|no_bits_sent_1_, uart_if_rom, 1
instance = comp, \inst|U1|u2|no_bits_sent_2_ , inst|U1|u2|no_bits_sent_2_, uart_if_rom, 1
instance = comp, \inst|U1|u2|no_bits_sent_3_ , inst|U1|u2|no_bits_sent_3_, uart_if_rom, 1
instance = comp, \inst|U1|u2|un17_clk1x_enable_a_Z , inst|U1|u2|un17_clk1x_enable_a_Z, uart_if_rom, 1
instance = comp, \inst|U1|u2|wrn2_i_Z , inst|U1|u2|wrn2_i_Z, uart_if_rom, 1
instance = comp, \inst|U1|u2|clk1x_enable_Z , inst|U1|u2|clk1x_enable_Z, uart_if_rom, 1
instance = comp, \inst|U1|u2|un1_clk1x_enable13_2_a_Z , inst|U1|u2|un1_clk1x_enable13_2_a_Z, uart_if_rom, 1
instance = comp, \inst|U1|u2|un1_clk1x_enable13_2 , inst|U1|u2|un1_clk1x_enable13_2, uart_if_rom, 1
instance = comp, \inst|U1|u2|tbre_0 , inst|U1|u2|tbre_0, uart_if_rom, 1
instance = comp, \~GND~I , ~GND, uart_if_rom, 1
instance = comp, \inst|rxd_in , inst|rxd_in, uart_if_rom, 1
instance = comp, \inst|U1|u1|rxd1_i_0_Z , inst|U1|u1|rxd1_i_0_Z, uart_if_rom, 1
instance = comp, \inst|U1|u1|no_bits_rcvd_1_ , inst|U1|u1|no_bits_rcvd_1_, uart_if_rom, 1
instance = comp, \inst|U1|u1|no_bits_rcvd_2_ , inst|U1|u1|no_bits_rcvd_2_, uart_if_rom, 1
instance = comp, \inst|U1|u1|rxd2_i_Z , inst|U1|u1|rxd2_i_Z, uart_if_rom, 1
instance = comp, \inst|U1|u1|clk1x_enable_0_Z , inst|U1|u1|clk1x_enable_0_Z, uart_if_rom, 1
instance = comp, \inst|U1|u1|no_bits_rcvd_0_ , inst|U1|u1|no_bits_rcvd_0_, uart_if_rom, 1
instance = comp, \inst|U1|u1|no_bits_rcvd_3_ , inst|U1|u1|no_bits_rcvd_3_, uart_if_rom, 1
instance = comp, \inst|U1|u1|un1_clk1x_enable13_0_a_Z , inst|U1|u1|un1_clk1x_enable13_0_a_Z, uart_if_rom, 1
instance = comp, \inst|U1|u1|parity8_0_x2_Z , inst|U1|u1|parity8_0_x2_Z, uart_if_rom, 1
instance = comp, \inst|U1|u1|rsr_7_ , inst|U1|u1|rsr_7_, uart_if_rom, 1
instance = comp, \inst|U1|u1|rsr_6_ , inst|U1|u1|rsr_6_, uart_if_rom, 1
instance = comp, \inst|U1|u1|rsr_5_ , inst|U1|u1|rsr_5_, uart_if_rom, 1
instance = comp, \inst|U1|u1|rsr_4_ , inst|U1|u1|rsr_4_, uart_if_rom, 1
instance = comp, \inst|U1|u1|rsr_3_ , inst|U1|u1|rsr_3_, uart_if_rom, 1
instance = comp, \inst|U1|u1|parity9_0_a3_Z , inst|U1|u1|parity9_0_a3_Z, uart_if_rom, 1
instance = comp, \inst|U1|u1|rbr_3_ , inst|U1|u1|rbr_3_, uart_if_rom, 1
instance = comp, \inst|U1|u1|un1_rst_i_a2_x , inst|U1|u1|un1_rst_i_a2_x, uart_if_rom, 1
instance = comp, \inst|U1|u1|data_ready12_0_a2_Z , inst|U1|u1|data_ready12_0_a2_Z, uart_if_rom, 1
instance = comp, \inst|U1|u1|data_ready_0 , inst|U1|u1|data_ready_0, uart_if_rom, 1
instance = comp, \inst|rdn_d_i_0_Z , inst|rdn_d_i_0_Z, uart_if_rom, 1
instance = comp, \inst|rdn_d2_i_Z , inst|rdn_d2_i_Z, uart_if_rom, 1
instance = comp, \inst|rdn_i_0_Z , inst|rdn_i_0_Z, uart_if_rom, 1
instance = comp, \inst|U1|u1|rbr_6_ , inst|U1|u1|rbr_6_, uart_if_rom, 1
instance = comp, \inst|U1|u1|rbr_5_ , inst|U1|u1|rbr_5_, uart_if_rom, 1
instance = comp, \inst|U1|u1|rbr_4_~I , inst|U1|u1|rbr_4_, uart_if_rom, 1
instance = comp, \inst|U1|u1|rbr_7_ , inst|U1|u1|rbr_7_, uart_if_rom, 1
instance = comp, \inst|U1|u1|rsr_2_ , inst|U1|u1|rsr_2_, uart_if_rom, 1
instance = comp, \inst|U1|u1|rsr_1_ , inst|U1|u1|rsr_1_, uart_if_rom, 1
instance = comp, \inst|U1|u1|rsr_0_ , inst|U1|u1|rsr_0_, uart_if_rom, 1
instance = comp, \inst|U1|u1|rbr_1_ , inst|U1|u1|rbr_1_, uart_if_rom, 1
instance = comp, \inst|U1|u1|rbr_0_~I , inst|U1|u1|rbr_0_, uart_if_rom, 1
instance = comp, \inst|U1|u1|rbr_2_ , inst|U1|u1|rbr_2_, uart_if_rom, 1
instance = comp, \inst|U1|u2|tsr14_Z , inst|U1|u2|tsr14_Z, uart_if_rom, 1
instance = comp, \inst|I_39_0_Z , inst|I_39_0_Z, uart_if_rom, 1
instance = comp, \inst|U1|u2|un13_tsre , inst|U1|u2|un13_tsre, uart_if_rom, 1
instance = comp, \inst|U1|u2|tsre_i_0 , inst|U1|u2|tsre_i_0, uart_if_rom, 1
instance = comp, \inst|un1_rom_addr9_3_i_a_Z , inst|un1_rom_addr9_3_i_a_Z, uart_if_rom, 1
instance = comp, \inst|un1_rom_addr9_3_i_Z , inst|un1_rom_addr9_3_i_Z, uart_if_rom, 1
instance = comp, \inst|rom_addr_d_0_ , inst|rom_addr_d_0_, uart_if_rom, 1
instance = comp, \inst|rom_addr_d_1_ , inst|rom_addr_d_1_, uart_if_rom, 1
instance = comp, \inst|rom_addr_d_2_ , inst|rom_addr_d_2_, uart_if_rom, 1
instance = comp, \inst|rom_addr_d_3_ , inst|rom_addr_d_3_, uart_if_rom, 1
instance = comp, \inst|rom_addr_d_4_ , inst|rom_addr_d_4_, uart_if_rom, 1
instance = comp, \inst|rom_addr_d_5_ , inst|rom_addr_d_5_, uart_if_rom, 1
instance = comp, \inst|rom_addr_d_6_ , inst|rom_addr_d_6_, uart_if_rom, 1
instance = comp, \inst|read_en_i_0_Z , inst|read_en_i_0_Z, uart_if_rom, 1
instance = comp, \inst|un1_read_en_2_i , inst|un1_read_en_2_i, uart_if_rom, 1
instance = comp, \inst|rom_addr_6_ , inst|rom_addr_6_, uart_if_rom, 1
instance = comp, \inst|rom_addr_5_ , inst|rom_addr_5_, uart_if_rom, 1
instance = comp, \inst|rom_addr_3_ , inst|rom_addr_3_, uart_if_rom, 1
instance = comp, \inst|rom_addr_1_ , inst|rom_addr_1_, uart_if_rom, 1
instance = comp, \inst|rom_addr_0_ , inst|rom_addr_0_, uart_if_rom, 1
instance = comp, \inst|rom_addr_4_ , inst|rom_addr_4_, uart_if_rom, 1
instance = comp, \inst|rom_addr_2_ , inst|rom_addr_2_, uart_if_rom, 1
instance = comp, \inst|un1_rdn_1_0_a4_a_Z , inst|un1_rdn_1_0_a4_a_Z, uart_if_rom, 1
instance = comp, \inst|un1_rdn_1_0_a4_Z , inst|un1_rdn_1_0_a4_Z, uart_if_rom, 1
instance = comp, \inst|un1_rdn_1_0_1 , inst|un1_rdn_1_0_1, uart_if_rom, 1
instance = comp, \inst|read_en_i , inst|read_en_i, uart_if_rom, 1
instance = comp, \inst|read_once_9_iv_i_0_a2_0_5_Z , inst|read_once_9_iv_i_0_a2_0_5_Z, uart_if_rom, 1
instance = comp, \inst|read_once_9_iv_i_0_a2_0_2_a_x_Z , inst|read_once_9_iv_i_0_a2_0_2_a_x_Z, uart_if_rom, 1
instance = comp, \inst|read_once_9_iv_i_0_a2_0_2_Z , inst|read_once_9_iv_i_0_a2_0_2_Z, uart_if_rom, 1
instance = comp, \inst|read_once_Z , inst|read_once_Z, uart_if_rom, 1
instance = comp, \inst|wrn_i_0_Z , inst|wrn_i_0_Z, uart_if_rom, 1
instance = comp, \inst|U1|u2|wrn1_i_0_Z , inst|U1|u2|wrn1_i_0_Z, uart_if_rom, 1
instance = comp, \inst|U1|u2|clkdiv_0_ , inst|U1|u2|clkdiv_0_, uart_if_rom, 1
instance = comp, \inst|U1|u2|clkdiv_5_sum3_a_Z , inst|U1|u2|clkdiv_5_sum3_a_Z, uart_if_rom, 1
instance = comp, \inst|U1|u2|clkdiv_1_ , inst|U1|u2|clkdiv_1_, uart_if_rom, 1
instance = comp, \inst|U1|u2|clkdiv_2_ , inst|U1|u2|clkdiv_2_, uart_if_rom, 1
instance = comp, \inst|U1|u2|clkdiv_3_ , inst|U1|u2|clkdiv_3_, uart_if_rom, 1
instance = comp, \inst|I_43_Z , inst|I_43_Z, uart_if_rom, 1
instance = comp, \MCLK~I , MCLK, uart_if_rom, 1
instance = comp, \inst1|altsyncram_component|auto_generated|ram_block1a0 , inst1|altsyncram_component|auto_generated|ram_block1a0, uart_if_rom, 1
instance = comp, \inst|din_7_ , inst|din_7_, uart_if_rom, 1
instance = comp, \inst|U1|u2|tbr_7_ , inst|U1|u2|tbr_7_, uart_if_rom, 1
instance = comp, \inst|U1|u2|un20_tsr , inst|U1|u2|un20_tsr, uart_if_rom, 1
instance = comp, \inst|U1|u2|tsr_7_ , inst|U1|u2|tsr_7_, uart_if_rom, 1
instance = comp, \inst|din_6_ , inst|din_6_, uart_if_rom, 1
instance = comp, \inst|U1|u2|tbr_6_ , inst|U1|u2|tbr_6_, uart_if_rom, 1
instance = comp, \inst|U1|u2|tsr_6_ , inst|U1|u2|tsr_6_, uart_if_rom, 1
instance = comp, \inst|din_5_ , inst|din_5_, uart_if_rom, 1
instance = comp, \inst|U1|u2|tbr_5_ , inst|U1|u2|tbr_5_, uart_if_rom, 1
instance = comp, \inst|U1|u2|tsr_5_ , inst|U1|u2|tsr_5_, uart_if_rom, 1
instance = comp, \inst|din_4_ , inst|din_4_, uart_if_rom, 1
instance = comp, \inst|U1|u2|tbr_4_ , inst|U1|u2|tbr_4_, uart_if_rom, 1
instance = comp, \inst|U1|u2|tsr_4_ , inst|U1|u2|tsr_4_, uart_if_rom, 1
instance = comp, \inst|din_3_ , inst|din_3_, uart_if_rom, 1
instance = comp, \inst|U1|u2|tbr_3_ , inst|U1|u2|tbr_3_, uart_if_rom, 1
instance = comp, \inst|U1|u2|tsr_3_ , inst|U1|u2|tsr_3_, uart_if_rom, 1
instance = comp, \inst|din_2_ , inst|din_2_, uart_if_rom, 1
instance = comp, \inst|U1|u2|tbr_2_ , inst|U1|u2|tbr_2_, uart_if_rom, 1
instance = comp, \inst|U1|u2|tsr_2_ , inst|U1|u2|tsr_2_, uart_if_rom, 1
instance = comp, \inst|din_1_ , inst|din_1_, uart_if_rom, 1
instance = comp, \inst|U1|u2|tbr_1_ , inst|U1|u2|tbr_1_, uart_if_rom, 1
instance = comp, \inst|U1|u2|tsr_1_ , inst|U1|u2|tsr_1_, uart_if_rom, 1
instance = comp, \inst|din_0_ , inst|din_0_, uart_if_rom, 1
instance = comp, \inst|U1|u2|tbr_0_ , inst|U1|u2|tbr_0_, uart_if_rom, 1
instance = comp, \inst|U1|u2|tsr_0_ , inst|U1|u2|tsr_0_, uart_if_rom, 1
instance = comp, \inst|U1|u2|tsr16_Z , inst|U1|u2|tsr16_Z, uart_if_rom, 1
instance = comp, \inst|U1|u2|parity_i_0 , inst|U1|u2|parity_i_0, uart_if_rom, 1
instance = comp, \inst|I_45_Z , inst|I_45_Z, uart_if_rom, 1
instance = comp, \inst|I_40_a_Z , inst|I_40_a_Z, uart_if_rom, 1
instance = comp, \inst|U1|u2|un1_tsr15_1_a_x_Z , inst|U1|u2|un1_tsr15_1_a_x_Z, uart_if_rom, 1
instance = comp, \inst|U1|u2|un1_tsr15_1_x , inst|U1|u2|un1_tsr15_1_x, uart_if_rom, 1
instance = comp, \inst|U1|u2|sdo_i_Z , inst|U1|u2|sdo_i_Z, uart_if_rom, 1
instance = comp, \inst|txd_out , inst|txd_out, uart_if_rom, 1