代码搜索：initial

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热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
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s heap.s

; ; Start of Zoran Standard Header ; Copyright (c) 2003 Zoran Corporation ; ; ; All rights reserved. Proprietary and confidential. ; ; DESCRIPTION for heap.s ; Support for
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c serial.c

#include "includes.h" /**************************************************************************** * Communications routines for the PC's serial port. These routines are * adapted from meth
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ini configure_sqlserver.ini

[Straight_Sqlserver] Provider=SQLOLEDB.1 Password= Persist Security Info=True User ID=sa Initial Catalog=TRAN_SH Data Source=127.0.0.1 [Aim_Sqlserver] Provider=SQLOLEDB.1 Persist Security I
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v fifotestbench.v

// -------------------------------------------------------------------- // >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE
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v clkgen.v

`timescale 1ns/10ps module cpu_clkg(fetch,clk2,clk,alu_clk); output fetch,clk2,clk,alu_clk; reg fetch,clk,clk2; parameter period=60; assign alu_clk=(fetch | clk2 | clk); initial fork
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m51 suma_ctst.m51

BL51 BANKED LINKER/LOCATER V5.03 08/31/2008 22:14:04 PAGE 1 BL51 BANKED LINKER/LOCATER V5.03, INVOKED BY: C:\KEIL\C51\BIN\BL51.EXE SUMA_C
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s asmcpu.s

# @(#) pSOSystem PowerPC/V2.2.2: bsps/fuc8xx/src/asmcpu.s * #************************************************************************ #
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lst main.lst

C51 COMPILER V7.02a MAIN 09/12/2008 14:50:31 PAGE 1 C51 COMPILER V7.02a, COMPILATION OF MODULE MAIN OBJECT MODULE PLACED IN m
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tf cnt99_tb.tf

module testbench(); // Inputs reg clk; reg reset; // Outputs wire [3:0] one_out; wire [3:0] ten_out; // Instantiate the UUT counter uut ( .clk(clk),
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tf demul1_4_if_tb.tf

module testbench(); // Inputs reg I; reg S0; reg S1; // Outputs wire [3:0] y; // Instantiate the UUT demul1_4_if uut ( .y(y), .I(I), .S0
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