clkgen.v

来自「关于FPGA的CPU的设计」· Verilog 代码 · 共 16 行

`timescale 1ns/10ps
 module cpu_clkg(fetch,clk2,clk,alu_clk);
  output fetch,clk2,clk,alu_clk;
  reg fetch,clk,clk2;
  parameter period=60;
  assign alu_clk=(fetch | clk2 | clk);
  initial
      fork
         clk=0;
         clk2=1;
         fetch=1;
         forever #(period/2) clk=~clk;
         forever #(period) clk2=~clk2;
         forever #(2*period) fetch=~fetch;
     join
 endmodule