cnt99_tb.tf

来自「FPGA开发板上写的Verilog代码： 功能是从电脑端发送一个字节」· TF 代码 · 共 38 行

module testbench();
// Inputs
    reg clk;
    reg reset;

// Outputs
    wire [3:0] one_out;
    wire [3:0] ten_out;

// Instantiate the UUT
    counter uut (
        .clk(clk), 
        .reset(reset), 
        .one_out(one_out), 
        .ten_out(ten_out)
        );

// Initialize Inputs
initial
 $monitor ($time, "clk=%b,  reset=%b, ten_out=%d, one_out=%d", clk, reset, ten_out, one_out);

initial	//Initialize input signals
 begin
    clk = 0;
    reset = 0;
  #35 reset=1;	         //Disable RESET at 35 units
 end

initial
 begin
   forever #10 clk=~clk;	//Set clock with a period 20 units
 end

initial #400 $finish;        //Complete simulation after 400 units

endmodule