demul1_4_if_tb.tf

FPGA开发板上写的Verilog代码： 功能是从电脑端发送一个字节

module testbench();
// Inputs
    reg I;
    reg S0;
    reg S1;
 
// Outputs
    wire [3:0] y;

// Instantiate the UUT
    demul1_4_if uut (
        .y(y), 
        .I(I), 
        .S0(S0), 
        .S1(S1)
        );



initial $monitor($time, "y = %b,  I = %b,  S0 = %b,  S1 = %b", y, I, S0, S1);
// Initialize Inputs
initial begin
  S0 = 1'b0;
  S1 = 1'b0;
  I = 1'b1;
end  

initial begin
  #20 S0 = 1'b1;
  #20 S0 = 1'b0;
  #20 S0 = 1'b1;
end
initial begin
  #20 S1 = 1'b0;
  #20 S1 = 1'b1;
  #20 S1 = 1'b1;
end

initial #100 $finish; //Complete simulation after 400 units

endmodule