代码搜索：initial
找到约 10,000 项符合「initial」的源代码
代码结果 10,000
www.eeworm.com/read/465315/7053046
v me_tf.v
`timescale 1 ns / 1 ns
module me_tf ;
reg [7:0] din ;
reg rst ;
reg clk ;
reg wr ;
wire mdo ;
wire ready ;
me u1 (rst,clk,wr,din,ready,mdo) ;
initial begin
rst = 1'b0 ;
clk = 1'b0 ;
din = 8'h0 ;
wr
www.eeworm.com/read/464646/7067085
cpp wordlist.cpp
#include
#include
#include
#include
using namespace std;
const int INITIAL_LIST_CAPACITY = 10;
void build_wordlist (string * &word_list, int &capaci
www.eeworm.com/read/366291/7068139
v clock_unit .v
module Clock_Unit (clock);
output clock;
reg clock;
parameter delay = 0;
parameter half_cycle = 10;
initial begin
#delay clock = 0;
forever #half_cycle clock = ~clock;
end
endmodule
www.eeworm.com/read/374790/7097662
hif paobiao.hif
Version 7.0 Build 33 02/05/2007 SJ Full Version
39
2288
OFF
OFF
OFF
OFF
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
--
www.eeworm.com/read/264839/7110918
v full_add1_tp.v
`timescale 1ns/1ns
module full_add1_tp();
reg a,b,cin;
wire sum,cout;
full_add1 inst_cnt(a,b,cin,sum,cout);
initial
begin
a=0;b=0;cin=0;
#10 a=0;b=0;cin=1;
#10 a=0;b=1;cin=0;
#10 a=0;b=
www.eeworm.com/read/264839/7110920
bak control_tp.v.bak
`timescale 1ns/1ns
module control_tp();
reg clk1,clk2;
wire reset;
wire[2:0] i;
wire OE;
control inst_cnt(clk1,clk2,i,OE,reset);
initial
begin
clk1=1;clk2=0;
#800 $stop;
end
always #5 clk2=~clk2;
www.eeworm.com/read/264839/7110943
v control_tp.v
`timescale 1ns/1ns
module control_tp();
reg clk1,clk2;
wire reset;
wire[2:0] i;
wire OE;
control inst_cnt(clk1,clk2,i,OE,reset);
initial
begin
clk1=1;clk2=1;
#800 $stop;
end
always #5 clk2=~clk2;
www.eeworm.com/read/264839/7110947
bak booth_tp.v.bak
`timescale 1ns/1ns
module booth_tp();
reg[2:0] i;
wire[2:0] b0,b1,b2,b3;
wire[7:0] H;
booth inst_cnt(i,H,b0,b1,b2,b3);
initial
begin
i=0;
#10 i=1;
#10 i=2;
#10 i=3;
#10 i=4;
#10 i=5
www.eeworm.com/read/264839/7110959
v half_add1_tp.v
`timescale 1ns/1ns
module half_add1_tp();
reg a,b;
wire sum,cout;
half_add1 inst_cnt(a,b,sum,cout);
initial
begin
a=0;b=0;
#10 a=0;b=1;
#10 a=1;b=0;
#10 a=1;b=1;
#10 $stop;
end
endmodul
www.eeworm.com/read/210887/7132709
lst main.lst
C51 COMPILER V7.06 MAIN 03/08/2006 13:20:04 PAGE 1
C51 COMPILER V7.06, COMPILATION OF MODULE MAIN
OBJECT MODULE PLACED IN ma