control_tp.v.bak

fpga功能实现有限字长响应FIR 用verilog编写

`timescale 1ns/1ns
module control_tp();
reg clk1,clk2;
wire reset;
wire[2:0] i;
wire OE;
control inst_cnt(clk1,clk2,i,OE,reset);
initial
begin
    clk1=1;clk2=0;

#800 $stop;
end
always #5 clk2=~clk2;
always #200 clk1=~clk1;
endmodule