booth_tp.v.bak

fpga功能实现有限字长响应FIR 用verilog编写

`timescale 1ns/1ns
module booth_tp();
reg[2:0] i;
wire[2:0] b0,b1,b2,b3;
wire[7:0] H;
booth  inst_cnt(i,H,b0,b1,b2,b3);
initial 
 begin
      i=0;
#10   i=1;
#10   i=2;
#10   i=3;
#10   i=4;
#10   i=5;
#10   i=6;
#10   i=7;
#10  $stop;
end
endmodule