代码搜索：dataflow
找到约 215 项符合「dataflow」的源代码
代码结果 215
www.eeworm.com/read/125617/14481959
c new bert.c
/* 511 code generator and Bit Error rate test */
#include "stdio.h"
#include "reg52.h"
#include
#define baudrate 9600
#define uartbaudrate 9600
#define Clock 33000000
sbit
www.eeworm.com/read/221024/14768146
edu^~hong^ http:^^www.cs.ucr.edu^~hong^
Date: Thu, 21 Nov 1996 20:03:17 GMT
Server: Apache/1.1.1
Content-type: text/html
Content-length: 1266
Last-modified: Wed, 15 Mar 1995 22:34:23 GMT
Yang-Chang Hong's Home Page
www.eeworm.com/read/290086/8506514
vhd votema.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY VoteMa IS
PORT(a,b,c:IN STD_LOGIC;
aa,bb,cc:OUT STD_LOGIC;
d:OUT STD_LOGIC);
END ENTITY VoteMa;
ARCHITECTURE dataflow OF VoteMa IS
SIGNA
www.eeworm.com/read/453446/7420398
lib decoder.lib
[~A]
last=1000
modifyid=3
valid=3071
ver=54
[~U]
dec24d=1000,5
dec24d__dataflow__code=0,1
www.eeworm.com/read/407957/11407047
vhd exdatafl.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture dataflow o
www.eeworm.com/read/300759/13894268
vhd onebitadder.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY onebitadder IS
PORT(x,y,cin:IN BIT;
sum,count:OUT BIT);
END onebitadder;
ARCHITECTURE dataflow OF onebitadder IS
BEGIN
sum
www.eeworm.com/read/290095/8505588
vhd halfadder.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY HalfAdder IS
PORT(dataA,dataB:IN STD_LOGIC;
carry,sum:OUT STD_LOGIC);
END ENTITY HalfAdder;
ARCHITECTURE dataflow OF HalfAdder IS
BEGIN
c
www.eeworm.com/read/186229/8951580
m bp_month.m
function [DataFore,DataReal,error]=BP_month(year,month,num,n)
% bp神经网络月径流预报
% year 待预报年
% month 待预报月份
% num 历史样本容量大小
% n 隐含层神经元个数
if (year-num-1)
www.eeworm.com/read/186229/8951585
m bp_year.m
function [DataFore,DataReal,error]=BP_year(year,num,n)
% bp神经网络年径流预报
% year 待预报年
% num 历史样本容量大小
% n 隐含层神经元个数
if (year-num-1)
www.eeworm.com/read/469852/6927992
txt bell.txt
library ieee;
use ieee.std_logic_1164.all;
entity bell is
port(bell1,bell2:in std_logic;
bellout:out std_logic);
end entity;
architecture dataflow of bell is
begin
bellout