代码搜索：dataflow
找到约 215 项符合「dataflow」的源代码
代码结果 215
www.eeworm.com/read/453446/7420400
log simulation.log
9:05 PM, Tuesday, March 31, 2009
Simulation has been initialized
Selected Top-Level: dec24d (dataflow)
Simulation has been stopped
www.eeworm.com/read/453446/7420402
log compile.log
Compilation...
File: .\src\VHDL code2.vhd
Compile Entity "dec24d"
Compile Architecture "dataflow" of Entity "dec24d"
Compile success 0 Errors 0 Warnings Analysis time : 0.0 [s]
www.eeworm.com/read/453446/7420406
erf decoder.erf
MESSAGE "File: .\src\VHDL code2.vhd"
MESSAGE "Compile Entity "dec24d""
MESSAGE "Compile Architecture "dataflow" of Entity "dec24d""
MESSAGE "Compile success 0 Errors 0 Warnings Analysis time :
www.eeworm.com/read/453446/7420407
lib~ contents.lib~
3
~E
dec24d
c:\my designs\decoder\src\VHDL code2.vhd
3
~A
dataflow
c:\my designs\decoder\src\VHDL code2.vhd
7
www.eeworm.com/read/453446/7420409
vhd vhdl code2.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dec24d IS
PORT(A,B,EN_L:IN BIT;
Q0,Q1,Q2,Q3:OUT BIT);
END ENTITY;
ARCHITECTURE dataflow OF dec24d IS
BEGIN
Q0
www.eeworm.com/read/453446/7420410
bak vhdl code2.bak
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dec24d IS
PORT(A,B,EN_L:IN BIT;
Q0,Q1,Q2,Q3:OUT BIT);
END ENTITY;
ARCHITECTURE dataflow OF dec24d IS
BEGIN
Q0
www.eeworm.com/read/298837/7931776
vhd halfadder.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY HalfAdder IS
PORT(dataA,dataB:IN STD_LOGIC;
carry,sum:OUT STD_LOGIC);
END ENTITY HalfAdder;
ARCHITECTURE dataflow OF HalfAdder IS
BEGIN
c
www.eeworm.com/read/478303/6714521
vhd ex_p4_23_cond_examplw.vhd
entity try is
end try;
architecture DATAFLOW of try is
signal a, b: bit;
signal c: bit_vector(1 downto 0);
begin
a
www.eeworm.com/read/262569/11399781
bak norgate.vhd.bak
Entity norgate is
generic (size: integer:=4);
Port (in1: in bit_vector ( size-1 downto 0);
in2: in bit_vector ( size-1 downto 0);
q: out bit_vector ( size-1 downto 0));
End norgate
www.eeworm.com/read/262569/11399802
vhd mux.vhd
Library IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.all;
USE IEEE.std_logic_arith.all;
Entity mux is
Port ( in1, in2, in3: in std_logic_vector( 3 downto