mux.vhd

vhdl 语言程序设计

Library IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.all;
USE IEEE.std_logic_arith.all;

Entity mux is 
 Port ( in1, in2, in3: in std_logic_vector( 3 downto 0);
        ctrl: in std_logic_vector ( 1 downto 0);
        q:    out  std_logic_vector( 3 downto 0));
End mux; 

Architecture dataflow of mux is 
 Begin 
  Process (in1, in2, in3, ctrl)
   Begin
      
    Case ctrl is 
     When "00" =>
       q<=in1;
     When "01" =>
       q<=in1;
     When "11" =>
       q<=in2;
     When "10" =>
       q<=in3;
     When others=>
         
     End case;
     
   End process;
 End dataflow;