代码搜索：dataIn

找到约 2,888 项符合「dataIn」的源代码

代码结果 2,888
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
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vhd mc14495.vhd

-- 七段锁存译码驱动器，不带小数点，如需显示小数点，则输出结果或”10000000“ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity mc14495 is port(datain:in std_logic_v
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vhd mc14495.vhd

-- 七段锁存译码驱动器，不带小数点，如需显示小数点，则输出结果或”10000000“ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity mc14495 is port(datain:in std_logic_v
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www.eeworm.com/read/380997/2650725

hier_info adc_0820.hier_info

|ADC_0820 cs_bar now_state~0.DATAB wr_rdy q0.DATAIN clk_state => q0.CLK clk
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hier_info ledwater.hier_info

|ledwater clk => pll20:u1.inclk0 sda => reg32[31].DATAIN sck => reg32[0].CLK sck => reg32[1].CLK sck => reg32[2].CLK sck => reg32[3].CLK sck => reg32[4].CLK sck => reg32[5].CLK sck => reg32[6
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www.eeworm.com/read/248277/12586559

vhd mc14495.vhd

-- 七段锁存译码驱动器，不带小数点，如需显示小数点，则输出结果或”10000000“ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity mc14495 is port(datain:in std_logic_v
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c 895sin.c

#include #define RESET P1_0 #define W_CLK P1_1 #define FQ_UD P1_2 #define datain P2 unsigned char word[5]={0x01,0x15,0x55,0x55,0x55}; unsigned char i; /*******************
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c ad.c

#include "msp430x22x4.h" #define ADCS_HIGH P2OUT |=BIT3 #define ADCS_LOW P2OUT &=~BIT3 #define ADCLK_HIGH P2OUT |=BIT1 #define ADCLK_LOW P2OUT &=~BIT1 #define DATAIN_IN P1IN &=BIT0 __n
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www.eeworm.com/read/281694/9139740

m dataindep.m

function [X] = DataIndep(kk,func1,func2,func3,func4,func5,func6) % [X] = DataIndep(k,func1,func2,func3,func4,func5,func6) % [X] = DataIndep(k,func1,func2,func3,func4,func5) % [X] = DataIn
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www.eeworm.com/read/450211/7488657

hier_info 2fsk_final.hier_info

|2fsk_final rd inst18.DATAIN din[0] => mx_7821:inst6.din[0] din[1] => mx_7821:inst6.din[1] din[2] => mx_7821:inst6.din[2] din[3] => mx_7821:inst6.din[3] din[4] => mx_
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www.eeworm.com/read/195920/8122957

hier_info dds_vhdl.hier_info

|DDS_VHDL CLK => sin_rom:u6.inclock CLK => reg10b:u5.Load CLK => sin_rom:u3.inclock CLK => reg32b:u2.Load CLK => CLK_DA.DATAIN CLK_DA adder32b:u1.A[20
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