adc_0820.hier_info

使用VHDL语言描述AD0809芯片功能

|ADC_0820
cs_bar <= <GND>
rd_bar <= rd_bar~reg0.DB_MAX_OUTPUT_PORT_TYPE
int_bar => Selector0.IN3
int_bar => now_state~0.DATAB
wr_rdy <= wr_rdy~0
clk_period => q0.DATAIN
clk_state => q0.CLK
clk_state => q1.CLK
clk_state => wr_bar.CLK
clk_state => rd_bar~reg0.CLK
clk_state => lock~reg0.CLK
clk_state => now_state~1.IN1
lock <= lock~reg0.DB_MAX_OUTPUT_PORT_TYPE