ledwater.hier_info

FPGA下的DDS程序的编写,VHDL语言,

|ledwater
clk => pll20:u1.inclk0
sda => reg32[31].DATAIN
sck => reg32[0].CLK
sck => reg32[1].CLK
sck => reg32[2].CLK
sck => reg32[3].CLK
sck => reg32[4].CLK
sck => reg32[5].CLK
sck => reg32[6].CLK
sck => reg32[7].CLK
sck => reg32[8].CLK
sck => reg32[9].CLK
sck => reg32[10].CLK
sck => reg32[11].CLK
sck => reg32[12].CLK
sck => reg32[13].CLK
sck => reg32[14].CLK
sck => reg32[15].CLK
sck => reg32[16].CLK
sck => reg32[17].CLK
sck => reg32[18].CLK
sck => reg32[19].CLK
sck => reg32[20].CLK
sck => reg32[21].CLK
sck => reg32[22].CLK
sck => reg32[23].CLK
sck => reg32[24].CLK
sck => reg32[25].CLK
sck => reg32[26].CLK
sck => reg32[27].CLK
sck => reg32[28].CLK
sck => reg32[29].CLK
sck => reg32[30].CLK
sck => reg32[31].CLK
DAC_CLK <= pll20:u1.c0
output[0] <= Ram0.DATAOUT
output[1] <= Ram0.DATAOUT1
output[2] <= Ram0.DATAOUT2
output[3] <= Ram0.DATAOUT3
output[4] <= Ram0.DATAOUT4
output[5] <= Ram0.DATAOUT5
output[6] <= Ram0.DATAOUT6
output[7] <= Ram0.DATAOUT7
output[8] <= Ram0.DATAOUT8
output[9] <= Ram0.DATAOUT9


|ledwater|pll20:u1
areset => altpll:altpll_component.areset
inclk0 => altpll:altpll_component.inclk[0]
c0 <= altpll:altpll_component.clk[0]
locked <= altpll:altpll_component.locked


|ledwater|pll20:u1|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => ~NO_FANOUT~
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => pll.ARESET
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanclkena => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
phasecounterselect[0] => ~NO_FANOUT~
phasecounterselect[1] => ~NO_FANOUT~
phasecounterselect[2] => ~NO_FANOUT~
phasecounterselect[3] => ~NO_FANOUT~
phaseupdown => ~NO_FANOUT~
phasestep => ~NO_FANOUT~
configupdate => ~NO_FANOUT~
clk[0] <= clk[0]~0.DB_MAX_OUTPUT_PORT_TYPE
clk[1] <= <GND>
clk[2] <= <GND>
clk[3] <= <GND>
clk[4] <= <GND>
clk[5] <= <GND>
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= pll.LOCKED
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE
phasedone <= <GND>
vcooverrange <= <GND>
vcounderrange <= <GND>
fbout <= <GND>