代码搜索：dataIn
找到约 2,888 项符合「dataIn」的源代码
代码结果 2,888
www.eeworm.com/read/175784/9532403
hier_info dff.hier_info
|dff2
clk => out_outp[0]~reg0.CLK
clk => out_outp[1]~reg0.CLK
in_outp[0] => out_outp[0]~reg0.DATAIN
in_outp[1] => out_outp[1]~reg0.DATAIN
out_outp[0]
www.eeworm.com/read/364280/9915620
bak segmain.vhd.bak
module seg78led(clk,reset_n,address,write_n,writedata,read_n,readdata,seg_data,seg_com);
input clk;
input reset_n;
//input chipselect;
input write_n;
input read_n;
input [2:0]address;
input [7:
www.eeworm.com/read/164302/10118714
hier_info reg32b.hier_info
|reg32b
load => dout[14]~reg0.CLK
load => dout[13]~reg0.CLK
load => dout[12]~reg0.CLK
load => dout[11]~reg0.CLK
load => dout[10]~reg0.CLK
load => dout[9]~reg0.CLK
load => dout[8]~reg0.CLK
load
www.eeworm.com/read/164302/10119014
hier_info fraq.hier_info
|fraq
fsin => cnt10:u2.clk
clk => oscdiv:u0.cp
clkled => dispscan:u11.clkdsp
resetled => dispscan:u11.reset
selled[0]
www.eeworm.com/read/164131/10128039
vhd sn7448.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sn7448 is
port(lt,rbi:std_logic;
datain:in std_logic_vector(3 downto 0);
rbo_b
www.eeworm.com/read/425799/10321579
bak sdfsm_tb.v.bak
/******************************************************************************
*
* LOGIC CORE: SDR SDRAM Controller test bench
* MODULE NAME: sdfsm_tb()
*
********************
www.eeworm.com/read/425799/10321710
v sdfsm_tb.v
/******************************************************************************
*
* LOGIC CORE: SDR SDRAM Controller test bench
* MODULE NAME: sdfsm_tb()
*
********************
www.eeworm.com/read/425799/10321722
v bwrite_s.v
`timescale 1ps / 1ps
module Bwrite_s
(
clk,
rst_n,
Bwrite_CE,
cmdack,
addr,
datain,
cmd,
Bfinish_W,
dm
);
input clk;
input rst_n;
input Bwrite_CE;/
www.eeworm.com/read/425799/10321762
bak bwrite_s.v.bak
`timescale 1ps / 1ps
module Bwrite_s
(
clk,
rst_n,
Bwrite_CE,
cmdack,
addr,
datain,
cmd,
Bfinish_W,
dm
);
input clk;
input rst_n;
input Bwrite_CE;/
www.eeworm.com/read/278232/10558269
v fpgab_top.v
`timescale 1ns / 1ps
module fpgab_top(clk, clk10, clk_out, reset_in,/*clk_data,clk_code,clk_fs,*/DA1_D,DA2_D,RST_DAC,DAC_SCLK,DAC_SDENB,
DAC_SDIO,DAC_SDO,DA_PLLLOCK,DAV1_B,DAV2_B