sdfsm_tb.v

一个RAM的测试仿真程序

/******************************************************************************
*
*  LOGIC CORE:          SDR SDRAM Controller test bench			
*  MODULE NAME:         sdfsm_tb()
*  
******************************************************************************/
`timescale 1ps / 1ps

module sdfsm_tb();
`include        "params.v"

//--------interface of main_top---------------------------------
reg                clk;   // Generated System Clock
reg                rst_n;
wire                cmdack;
wire      [15:0]   dataout;
wire      [2:0]    cmd;
wire      [22:0]   addr;
wire      [15:0]    datain;
wire      [1:0]    dm;
wire      [3:0]    toLED;




//--------interface of sd_sdram---------------------------------

wire      [11:0]   sa;
wire      [1:0]    ba;
wire      [1:0]    cs_n;
wire               cke;
wire               ras_n;
wire               cas_n;
wire               we_n;
wire      [15:0]   dq;
wire      [1:0]    dqm;

//--------interface of mt48lc---------------------------------
//wire cs_n0;
reg  clk2;
assign cs_n = 0;//dont use cs.

//-----main_top-------------------------------------------------
main_top main_top1 (
                     .clk(clk),
                     .rst_n(rst_n),
                     .cmdack(cmdack),
                     .dataout(dataout),
                     .cmd(cmd),
                     .addr(addr),
                     .datain(datain),
                     .dm(dm),
                     .toLED(toLED)
                    );
                     

// SDR SDRAM controller
sdr_sdram sdr_sdram1 (
                .CLK(clk),
                .RESET_N(rst_n),
                .ADDR(addr),
                .CMD(cmd),
                .CMDACK(cmdack),
                .DATAIN(datain),
                .DATAOUT(dataout),
                .DM(dm),
                .SA(sa),
                .BA(ba),
                .CS_N(cs_n),
                .CKE(cke),
                .RAS_N(ras_n),
                .CAS_N(cas_n),
                .WE_N(we_n),
                .DQ(dq),
                .DQM(dqm)
                );

// micron memory models

mt48lc8m16a2 mem00      (.Dq(dq[15:0]),
                        .Addr(sa[11:0]),
                        .Ba(ba),
                        .Clk(clk2),
                        .Cke(cke),
                        .Cs_n(cs_n[0]),
                        .Cas_n(cas_n),
                        .Ras_n(ras_n),
                        .We_n(we_n),
                        .Dqm(dqm[1:0]));

                        


initial begin
        clk = 1;
        clk2 = 1;
        rst_n = 0;                                             // reset the system
        #100000 rst_n = 1;
end


// system clocks

//133mhz clock always block
always begin
        #2750 clk2 = ~clk2;                                  
        #1000 clk = ~clk;
end


//  $stop;
endmodule