代码搜索:dataIn

找到约 2,888 项符合「dataIn」的源代码

代码结果 2,888
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hier_info weifenqi.hier_info

|weifenqi codeout inst1.IN0 codein => inst.IN0 codein => yicunqi:inst5.Din clkin => yicunqi:inst5.clk |weifenqi|yicunqi:inst5 Dout
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vhd reg.vhd

--------------------------------锁存器用于锁存闹钟数据 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity reg is port(lock : in std_logic; DataIn0,DataIn1 : in std_
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pcf top.pcf

SCHEMATIC START ; // created by map version G.26 on Thu May 08 16:23:39 2008 COMP "SINE2" LOCATE = SITE "P205" LEVEL 1; COMP "DataIN" LOCATE = SITE "P37" LEVEL 1; COMP "DataIN" LOCA
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txt 水位(定).txt

//////////////////////////////////////////////////////// // MODEL:watherhighcheck // // MCU:AT89C2051 // // Ctystal:1
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vhd tribuffer.vhd

library ieee; use ieee.std_logic_1164.all; ------------------------------ entity tribuffer is port (oe:in std_logic; datain:in std_logic_vector(7 downto 0); dataout:out std_logic_vector(7 downt
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c key.c

#include "uPSD3300.h" #include "TurboLite_hardware.h" #include "Turbo_timer.h" extern xdata PSD_REGS PSD8xx_reg; unsigned char Key_check() { //PSD8xx_reg.DRIVE_D|=0x06; // OpenDra
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vhd testda.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity testda is port(clk:in std_logic; data:out std_logic_vector(7 downto 0);
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vhd dataoutmux.vhd

--**************************************************************************************************** -- Data out register for ARM core -- Designed by Ruslan Lepetenok -- Modified 04.12.2002 --**
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vhd resltbitmask.vhd

--**************************************************************************************************** -- This module cleares/sets bit 0 and clears 1 of ALU bus for ARM7TDMI-S processor -- Designed
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hier_info top.hier_info

|top full clk_div:inst3.clkin clk_cpu => clk_select:inst2.clk_cpu rst => com:inst.rst change => com:inst.change datain[0] => com:inst.datain[0] datain[1]