testda.vhd

硬件电子琴系统设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity testda is 
	port(clk:in std_logic;	
		 data:out std_logic_vector(7 downto 0);
		 ad_cs:out std_logic
			);
end testda;
architecture behave of testda is 
--signal 
		begin
 process(clk)
	variable flag:std_logic:='0';
	variable datain:std_logic_vector(7 downto 0):="00000000";
begin
if(clk'event and clk='1')then
	flag:=not flag;
	if(flag='1')then
		datain:="00000001";
	else
		datain:="00000000";
	end if;
end if;
data<=datain;
ad_cs<='1';
end process;
end behave;