top.hier_info

基于FPGA有限状态机的数据采集系统

|top
full <= fu.DB_MAX_OUTPUT_PORT_TYPE
clkin => clk_div:inst3.clkin
clk_cpu => clk_select:inst2.clk_cpu
rst => com:inst.rst
change => com:inst.change
datain[0] => com:inst.datain[0]
datain[1] => com:inst.datain[1]
datain[2] => com:inst.datain[2]
datain[3] => com:inst.datain[3]
datain[4] => com:inst.datain[4]
datain[5] => com:inst.datain[5]
datain[6] => com:inst.datain[6]
datain[7] => com:inst.datain[7]
dataram[0] <= com:inst.dataram[0]
dataram[1] <= com:inst.dataram[1]
dataram[2] <= com:inst.dataram[2]
dataram[3] <= com:inst.dataram[3]
dataram[4] <= com:inst.dataram[4]
dataram[5] <= com:inst.dataram[5]
dataram[6] <= com:inst.dataram[6]
dataram[7] <= com:inst.dataram[7]
ready <= com:inst.ready
adclk <= com:inst.adclk
wr_ram <= com:inst.wr_ram
rd_ram <= com:inst.rd_ram
clk_test <= clk_select:inst2.clk
addre[0] <= addre:inst1.addre[0]
addre[1] <= addre:inst1.addre[1]
addre[2] <= addre:inst1.addre[2]
addre[3] <= addre:inst1.addre[3]
addre[4] <= addre:inst1.addre[4]
addre[5] <= addre:inst1.addre[5]
addre[6] <= addre:inst1.addre[6]
addre[7] <= addre:inst1.addre[7]
addre[8] <= addre:inst1.addre[8]
addre[9] <= addre:inst1.addre[9]
addre[10] <= addre:inst1.addre[10]
addre[11] <= addre:inst1.addre[11]
addre[12] <= addre:inst1.addre[12]
addre[13] <= addre:inst1.addre[13]
addre[14] <= addre:inst1.addre[14]
addre[15] <= addre:inst1.addre[15]
addre[16] <= addre:inst1.addre[16]
addre[17] <= addre:inst1.addre[17]
dataout[0] <= com:inst.dataout[0]
dataout[1] <= com:inst.dataout[1]
dataout[2] <= com:inst.dataout[2]
dataout[3] <= com:inst.dataout[3]
dataout[4] <= com:inst.dataout[4]
dataout[5] <= com:inst.dataout[5]
dataout[6] <= com:inst.dataout[6]
dataout[7] <= com:inst.dataout[7]
st[0] <= com:inst.st[0]
st[1] <= com:inst.st[1]


|top|addre:inst1
clk => full_temp.CLK
clk => count[0].CLK
clk => count[1].CLK
clk => count[2].CLK
clk => count[3].CLK
clk => count[4].CLK
clk => count[5].CLK
clk => count[6].CLK
clk => count[7].CLK
clk => count[8].CLK
clk => count[9].CLK
clk => count[10].CLK
clk => count[11].CLK
clk => count[12].CLK
clk => count[13].CLK
clk => count[14].CLK
clk => count[15].CLK
clk => count[16].CLK
clk => count[17].CLK
flag => count~18.OUTPUTSELECT
flag => count~19.OUTPUTSELECT
flag => count~20.OUTPUTSELECT
flag => count~21.OUTPUTSELECT
flag => count~22.OUTPUTSELECT
flag => count~23.OUTPUTSELECT
flag => count~24.OUTPUTSELECT
flag => count~25.OUTPUTSELECT
flag => count~26.OUTPUTSELECT
flag => count~27.OUTPUTSELECT
flag => count~28.OUTPUTSELECT
flag => count~29.OUTPUTSELECT
flag => count~30.OUTPUTSELECT
flag => count~31.OUTPUTSELECT
flag => count~32.OUTPUTSELECT
flag => count~33.OUTPUTSELECT
flag => count~34.OUTPUTSELECT
flag => count~35.OUTPUTSELECT
flag => full_temp~0.OUTPUTSELECT
flag => full_temp.ALOAD
flag => count[17].ALOAD
flag => count[16].ALOAD
flag => count[15].ALOAD
flag => count[14].ALOAD
flag => count[13].ALOAD
flag => count[12].ALOAD
flag => count[11].ALOAD
flag => count[10].ALOAD
flag => count[9].ALOAD
flag => count[8].ALOAD
flag => count[7].ALOAD
flag => count[6].ALOAD
flag => count[5].ALOAD
flag => count[4].ALOAD
flag => count[3].ALOAD
flag => count[2].ALOAD
flag => count[1].ALOAD
flag => count[0].ALOAD
full <= full_temp.DB_MAX_OUTPUT_PORT_TYPE
addre[0] <= count[0].DB_MAX_OUTPUT_PORT_TYPE
addre[1] <= count[1].DB_MAX_OUTPUT_PORT_TYPE
addre[2] <= count[2].DB_MAX_OUTPUT_PORT_TYPE
addre[3] <= count[3].DB_MAX_OUTPUT_PORT_TYPE
addre[4] <= count[4].DB_MAX_OUTPUT_PORT_TYPE
addre[5] <= count[5].DB_MAX_OUTPUT_PORT_TYPE
addre[6] <= count[6].DB_MAX_OUTPUT_PORT_TYPE
addre[7] <= count[7].DB_MAX_OUTPUT_PORT_TYPE
addre[8] <= count[8].DB_MAX_OUTPUT_PORT_TYPE
addre[9] <= count[9].DB_MAX_OUTPUT_PORT_TYPE
addre[10] <= count[10].DB_MAX_OUTPUT_PORT_TYPE
addre[11] <= count[11].DB_MAX_OUTPUT_PORT_TYPE
addre[12] <= count[12].DB_MAX_OUTPUT_PORT_TYPE
addre[13] <= count[13].DB_MAX_OUTPUT_PORT_TYPE
addre[14] <= count[14].DB_MAX_OUTPUT_PORT_TYPE
addre[15] <= count[15].DB_MAX_OUTPUT_PORT_TYPE
addre[16] <= count[16].DB_MAX_OUTPUT_PORT_TYPE
addre[17] <= count[17].DB_MAX_OUTPUT_PORT_TYPE


|top|clk_select:inst2
clk_sys => clk~1.DATAB
clk_cpu => clk~0.DATAB
clk_s => clk~0.OUTPUTSELECT
clk_s => clk~1.OUTPUTSELECT
clk <= clk~1.DB_MAX_OUTPUT_PORT_TYPE


|top|clk_div:inst3
clkin => clk_temp.CLK
clkin => count[0].CLK
clkin => count[1].CLK
clkin => count[2].CLK
clkin => count[3].CLK
clk <= clk_temp.DB_MAX_OUTPUT_PORT_TYPE


|top|com:inst
clk => adclk~0.DATAB
clk => wr_ram~0.DATAB
clk => rd_ram~0.DATAB
clk => current_state~0.IN1
rst => Selector0.IN2
rst => Selector3.IN2
rst => Selector1.IN1
rst => current_state~1.IN1
full => Selector1.IN3
full => Selector2.IN1
change => Selector2.IN3
change => Selector3.IN1
datain[0] => dataram[0]$latch.DATAIN
datain[1] => dataram[1]$latch.DATAIN
datain[2] => dataram[2]$latch.DATAIN
datain[3] => dataram[3]$latch.DATAIN
datain[4] => dataram[4]$latch.DATAIN
datain[5] => dataram[5]$latch.DATAIN
datain[6] => dataram[6]$latch.DATAIN
datain[7] => dataram[7]$latch.DATAIN
flag <= flag~0.DB_MAX_OUTPUT_PORT_TYPE
ready <= ready~0.DB_MAX_OUTPUT_PORT_TYPE
adclk <= adclk~0.DB_MAX_OUTPUT_PORT_TYPE
wr_ram <= wr_ram~0.DB_MAX_OUTPUT_PORT_TYPE
rd_ram <= rd_ram~0.DB_MAX_OUTPUT_PORT_TYPE
st[0] <= flag~0.DB_MAX_OUTPUT_PORT_TYPE
st[1] <= ready~0.DB_MAX_OUTPUT_PORT_TYPE
dataram[0] <= comb~8
dataram[1] <= comb~9
dataram[2] <= comb~10
dataram[3] <= comb~11
dataram[4] <= comb~12
dataram[5] <= comb~13
dataram[6] <= comb~14
dataram[7] <= comb~15
dataout[0] <= comb~7.DB_MAX_OUTPUT_PORT_TYPE
dataout[1] <= comb~6.DB_MAX_OUTPUT_PORT_TYPE
dataout[2] <= comb~5.DB_MAX_OUTPUT_PORT_TYPE
dataout[3] <= comb~4.DB_MAX_OUTPUT_PORT_TYPE
dataout[4] <= comb~3.DB_MAX_OUTPUT_PORT_TYPE
dataout[5] <= comb~2.DB_MAX_OUTPUT_PORT_TYPE
dataout[6] <= comb~1.DB_MAX_OUTPUT_PORT_TYPE
dataout[7] <= comb~0.DB_MAX_OUTPUT_PORT_TYPE
clk_s <= current_state.s3.DB_MAX_OUTPUT_PORT_TYPE