reg.vhd

来自「一个用vhdl写的时钟代码」· VHDL 代码 · 共 25 行

--------------------------------锁存器用于锁存闹钟数据
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity reg is
  port(lock : in std_logic;
       DataIn0,DataIn1 : in std_logic_vector(3 downto 0); 
		DataIn2,DataIn3 : in std_logic_vector(3 downto 0);
		DataOut0,DataOut1 : out std_logic_vector(3 downto 0);
		DataOut2,DataOut3 : out std_logic_vector(3 downto 0));
 end entity reg;
-------------------------------------------------
architecture behave of reg is
  begin
	process(lock,DataIn0,DataIn1,
			DataIn2,DataIn3)
	begin
	if lock'event and lock='1' then 
	 DataOut0 <= DataIn0;
	 DataOut1 <= DataIn1;
	 DataOut2<= DataIn2;
	 DataOut3 <= DataIn3;
	end if;
	end process;
end architecture behave;