代码搜索：dataIn

找到约 2,888 项符合「dataIn」的源代码

代码结果 2,888
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/141583/12996968

v sdram_port.v

/********************************************************* MODULE: Sub Level Controller, SDRAM Data Port FILE NAME: sdram_port.v VERSION: 1.0 DATE: April 28th, 2002 AUTHOR: Hossein Amid
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www.eeworm.com/read/328146/13044797

vhd uarttest.vhd

--============================================================================-- -- Design units : TestBench for miniUART device. -- -- File name : UARTTest.vhd -- -- Purpose : Implemen
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www.eeworm.com/read/139313/13163467

vhd divid.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity divid is port (testin:in std_logic_vector(4 downto 0); datain:in std_logic_vector(7 downto 0); test
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www.eeworm.com/read/325485/13201391

asm bf533_config.asm

/******************************************************************************/ // // Name: BF533 EZ-KIT video ITU-656 8bit receive mode // /*****************************************************
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www.eeworm.com/read/137918/13279676

rpt mcs_51.fit.rpt

Fitter report for mcs_51 Sat Aug 13 15:32:51 2005 Version 4.2 Build 157 12/07/2004 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. F
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www.eeworm.com/read/137601/13309906

sdo step_motor_vhd.sdo

// Copyright (C) 1991-2005 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and
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www.eeworm.com/read/137601/13309978

sdo step_motor_vhd.sdo

// Copyright (C) 1991-2005 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and
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www.eeworm.com/read/319967/13438315

hier_info adc.hier_info

|adc clk => clkcount[2].CLK clk => clkcount[1].CLK clk => clkcount[0].CLK clk => count.CLK clk => clkcount[3].CLK int => fsm1~0.IN1 dati[0] => data[0].DATAIN dati[1] => data[1].DATAIN dati[2]
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www.eeworm.com/read/318340/13481090

hier_info lcd1.hier_info

|lcd1 clk => st.CLK clk => data[0]~reg0.CLK clk => data[0]~en.CLK clk => data[1]~reg0.CLK clk => data[1]~en.CLK clk => data[2]~reg0.CLK clk => data[2]~en.CLK clk => data[3]~reg0.CLK clk => da
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www.eeworm.com/read/311947/13620938

vhd uarttest.vhd

--============================================================================-- -- Design units : TestBench for miniUART device. -- -- File name : UARTTest.vhd -- -- Purpose : Implemen
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