代码搜索：dataIn
找到约 2,888 项符合「dataIn」的源代码
代码结果 2,888
www.eeworm.com/read/371886/9532080
vhd uarttest.vhd
--============================================================================--
-- Design units : TestBench for miniUART device.
--
-- File name : UARTTest.vhd
--
-- Purpose : Imp
www.eeworm.com/read/366351/9820103
qmsg vhdl5.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
www.eeworm.com/read/363302/9960714
vhd mux6_1.vhd
library ieee;
use ieee.std_logic_1164.all;
entity mux6_1 is
port(
sel : in std_logic_vector(2 downto 0);
clk : in std_logic;
datain : in std_logic_vector(9 downto 0);
d
www.eeworm.com/read/301737/10047981
vhd rs232_t.vhd
--the rs232 send module
--include one clk and one send component
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
entity rs232_t is --send and pll1的物理连接
p
www.eeworm.com/read/357005/10217691
vhd testda.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity testda is
port(clk:in std_logic;
data:out std_logic_vector(7 downto 0);
www.eeworm.com/read/426301/10266789
vhd moore1.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MOORE1 IS
PORT (DATAIN : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
CLK,RST:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END MOOR
www.eeworm.com/read/422910/10603525
v data_port.v
/*********************************************************
MODULE: Sub Level SDRAM Controller Data Port Block
FILE NAME: data_port.v
VERSION: 1.0
DATE: April 8nd, 2002
AUTHOR: Hossein Amidi
www.eeworm.com/read/422910/10603575
v sdram_port.v
/*********************************************************
MODULE: Sub Level Controller, SDRAM Data Port
FILE NAME: sdram_port.v
VERSION: 1.0
DATE: April 28th, 2002
AUTHOR: Hossein Amidi
COM
www.eeworm.com/read/349548/10818788
vhd testda.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity testda is
port(clk:in std_logic;
data:out std_logic_vector(7 downto 0);
www.eeworm.com/read/349383/10831502
vhd dpram.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dpram is
end entity;
architecture Behavioral of dpram is
constant delay : ti