vhdl5.map.qmsg

程序提供了一种简单高效的并入串出寄存器的算法

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 03 01:29:41 2008 " "Info: Processing started: Thu Jan 03 01:29:41 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off vhdl5 -c vhdl5 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off vhdl5 -c vhdl5" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Vhdl5.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Vhdl5.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 vhdl5-BEHAV " "Info: Found design unit 1: vhdl5-BEHAV" {  } { { "Vhdl5.vhd" "" { Text "E:/new vhdl/vhdl5/Vhdl5.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 vhdl5 " "Info: Found entity 1: vhdl5" {  } { { "Vhdl5.vhd" "" { Text "E:/new vhdl/vhdl5/Vhdl5.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "vhdl5 " "Info: Elaborating entity \"vhdl5\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "DATAIN Vhdl5.vhd(18) " "Warning (10492): VHDL Process Statement warning at Vhdl5.vhd(18): signal \"DATAIN\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Vhdl5.vhd" "" { Text "E:/new vhdl/vhdl5/Vhdl5.vhd" 18 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "6 " "Warning: Design contains 6 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "DATAIN\[1\] " "Warning: No output dependent on input pin \"DATAIN\[1\]\"" {  } { { "Vhdl5.vhd" "" { Text "E:/new vhdl/vhdl5/Vhdl5.vhd" 6 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "DATAIN\[2\] " "Warning: No output dependent on input pin \"DATAIN\[2\]\"" {  } { { "Vhdl5.vhd" "" { Text "E:/new vhdl/vhdl5/Vhdl5.vhd" 6 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "DATAIN\[3\] " "Warning: No output dependent on input pin \"DATAIN\[3\]\"" {  } { { "Vhdl5.vhd" "" { Text "E:/new vhdl/vhdl5/Vhdl5.vhd" 6 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "DATAIN\[4\] " "Warning: No output dependent on input pin \"DATAIN\[4\]\"" {  } { { "Vhdl5.vhd" "" { Text "E:/new vhdl/vhdl5/Vhdl5.vhd" 6 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "DATAIN\[5\] " "Warning: No output dependent on input pin \"DATAIN\[5\]\"" {  } { { "Vhdl5.vhd" "" { Text "E:/new vhdl/vhdl5/Vhdl5.vhd" 6 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "DATAIN\[6\] " "Warning: No output dependent on input pin \"DATAIN\[6\]\"" {  } { { "Vhdl5.vhd" "" { Text "E:/new vhdl/vhdl5/Vhdl5.vhd" 6 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "14 " "Info: Implemented 14 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "10 " "Info: Implemented 10 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "3 " "Info: Implemented 3 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 8 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 03 01:29:42 2008 " "Info: Processing ended: Thu Jan 03 01:29:42 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}