dpram.vhd

利用vhdl编写的双端口Ram程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity dpram is
end entity;

architecture Behavioral of dpram is
constant delay : time  := 3 ns;
constant width : positive := 16;
constant depth : positive := 8;  
signal clka : std_logic;
signal wr  : std_logic;
signal addra : std_logic_vector(7 downto 0)  := "00000000";
signal datain : std_logic_vector(15 downto 0) := x"0002";

signal clkb : std_logic;
signal rd  : std_logic;
signal addrb : std_logic_vector(7 downto 0) := "00000000";
signal dataout : std_logic_vector(15 downto 0);

component dpram
-- generic 
-- (
--  width : positive := 16;
--  depth : positive := 8
-- );
 port
 (
  ------------------------- port a is only for writing -------------------------------
  clka : in std_logic;
  wr  : in std_logic;
  addra : in std_logic_vector(depth - 1 downto 0);
  datain : in std_logic_vector(width - 1 downto 0);
  ------------------------------------------------------------------------------------
  ------------------------- port b is only for reading -------------------------------
  clkb : in std_logic;
  rd  : in std_logic;
  addrb : in std_logic_vector(depth - 1 downto 0);
  dataout : out std_logic_vector(width - 1 downto 0)  
  ------------------------------------------------------------------------------------
 );
end component;

begin
 ----------------------------------------------------------------------------------------
 tb : dpram
-- generic map
-- (
--  width,
--  depth
-- )
 port map
 (
  clka => clka,     
  wr  => wr,  
  addra => addra, 
  datain => datain, 
  --------=> -------- 
  --------=> -------- 
  clkb => clkb,     
  rd  => rd,  
  addrb => addrb, 
  dataout => dataout 
 );
 ----------------------------------------------------------------------------------------
 
 ----------------------------------------------------------------------------------------
 process
 begin
  clka <= '0';
	wait for 13 ns;
  loop
   clka <= not clka;
   wait for 10 ns;
  end loop;
 end process;
 
 process
 begin
  clkb <= '0';
  wait for 12 ns;
  loop
   clkb <= not clkb;
   wait for 7 ns;
  end loop; 
 end process;

 process
 begin
  wr <= '1';
  rd <= '1';
  wait for 24 ns;
  wr <= '0';
  wait for 60 ns;
  rd <= '0';
  wait for 300 ns;
  wr <= '1';
  wait;
 end process;
 
 process(clka)
 begin
  if clka'event and clka = '1' then
   if wr = '0' then
    addra <= addra + 1 after delay;
   end if;
   datain<= datain + 1 after delay;
  end if;
 end process;
 
 process(clkb)
 begin
  if clkb'event and clkb = '1' then
   if rd = '0' then
    addrb <= addrb + 1 after delay;
   end if;
  end if;
 end process;
end Behavioral;