代码搜索：dataIn
找到约 2,888 项符合「dataIn」的源代码
代码结果 2,888
www.eeworm.com/read/177025/9474141
c pseudo_channel.c
/*****************************************************************************/
/* FIle Name : pseudo_channel.c */
/* Description : WLAN Pseudo Channel E
www.eeworm.com/read/177025/9474154
c interleaver.c
/*****************************************************************************/
/* FIle Name : interleaver.c */
/* Description : WLAN FEC interleaver
www.eeworm.com/read/177025/9474168
c deinterleaver.c
/*****************************************************************************/
/* FIle Name : deinterleaver.c */
/* Description : WLAN FEC deinterleave
www.eeworm.com/read/176962/9478850
txt data converter.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity data_convert is
generic(
DSIZE :integer:=32;
MSPDATA :integer:=8
);
port
www.eeworm.com/read/364280/9914341
vhd segmain.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity segmain is
PORT( clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
datain : IN STD_LOGIC_VECTOR(15 DO
www.eeworm.com/read/364280/9915073
rpt tt.tan.rpt
Classic Timing Analyzer report for tt
Fri Jan 11 02:18:42 2008
Quartus II Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version
---------------------
; Table of Contents ;
---------
www.eeworm.com/read/360577/10086958
txt des_3.txt
module des_3(sysclk,en,reset,load,mode1,mode2,mode3,datain,key1,key2,key3,ready,dataout);
input[64:1] key1,key2,key3,datain;
input sysclk,en,reset,mode1,mode2,mode3,load;
output ready;
output[64:1
www.eeworm.com/read/425799/10321713
v config_s.v
`timescale 1ps / 1ps
module config_s
(
clk,
rst_n,
config_CE,
cmdack,
addr,
datain,
cmd,
finish_F
);
input clk;
input rst_n;
input config_CE;//高电平
www.eeworm.com/read/354540/10346849
demo_hier_info
|demo
rs232out fen1250:inst.clk
|demo|serialout:inst3
clk => qinbuf[7].CLK
clk => qinbuf[6].CLK
clk => qinbuf[5].CLK
clk => qinbuf[4].CLK
clk => qinbuf[3].CLK