segmain.vhd

来自「Verilog 经典实例」· VHDL 代码 · 共 52 行

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity segmain is
 PORT( clk  :  IN  STD_LOGIC;
       rst  :  IN  STD_LOGIC;
    datain  :  IN STD_LOGIC_VECTOR(15 DOWNTO 0);
    dataout :  OUT STD_LOGIC_VECTOR(3 downto 0);
    ledcom  :  OUT STD_LOGIC_VECTOR(3 downto 0)
 );
END segmain;
ARCHITECTURE behav OF segmain IS
  
  SIGNAL comclk   :  STD_LOGIC_VECTOR(1 DOWNTO 0);
  SIGNAL bcd_led  :  STD_LOGIC_VECTOR(3 DOWNTO 0);
  
begin
  process(rst,clk)
begin
 if rst='1' then
   comclk<="00";
  elsif rising_edge(clk) then
       if comclk>=3 then
         comclk<="00";
        else
          comclk<=comclk+1;
        end if;
       end if;

end process;
process(comclk)
 begin
     if     comclk="00" then ledcom<="0001";
     elsif  comclk="01" then ledcom<="0010";
     elsif  comclk="10" then ledcom<="0100";
     else  ledcom<="1000";
     end if;
end process;
process(comclk)
 begin
    if     comclk="00" then bcd_led<=datain(3 downto 0);
    elsif  comclk="01" then bcd_led<=datain(7 downto 4);
    elsif  comclk="10" then bcd_led<=datain(11 downto 8);
    else   bcd_led<=datain(15 downto 12);end if;
end process;

dataout<=bcd_led;

end behav;