data converter.txt

利用VHDL语言实现8位到32位的双向数据转换

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity data_convert  is
 generic(
          DSIZE     :integer:=32;
          MSPDATA   :integer:=8
         );
 port(
           CLK      :in     std_logic;
           DATAIN   :out    std_logic_vector(DSIZE-1 downto 0);
           DATAOUT  :in     std_logic_vector(DSIZE-1 downto 0);
           DATA     :inout  std_logic_vector(MSPDATA-1 downto 0);
           WR       :in     std_logic
        );
end data_convert;

architecture behavioral of data_convert  is
signal temp_datain :std_logic_vector(31 downto 0);
signal cnt2b1 :integer RANGE 0 TO 3;
signal cnt2b2 :integer RANGE 0 TO 3;

begin 
p1: process(WR,CLK)
      begin
     if CLK'event AND CLK='1'  THEN
       if WR = '1' THEN
        cnt2b1<=cnt2b1+1;
       end if;
     end if;
end process;

p2:process(cnt2b1)
    begin
   if WR = '1' THEN
       case cnt2b1 is

       when 0 => temp_datain(7 downto 0)  <=DATA(MSPDATA-1 downto 0);
       when 1 => temp_datain(15 downto 8) <=DATA(MSPDATA-1 downto 0);
       when 2 => temp_datain(23 downto 16)<=DATA(MSPDATA-1 downto 0);
       when 3 => temp_datain(31 downto 24)<=DATA(MSPDATA-1 downto 0);
       when others => temp_datain(7 downto 0)<="11111111";
     end case;
    DATAIN(31 downto 0)<=temp_datain(31 downto 0)   ;
     end if;
 end process;

p11: process(WR,CLK)
      begin
     if CLK'event AND CLK='1'  THEN
       if WR = '0' THEN
        cnt2b2<=cnt2b2+1;
       end if;
     end if;
end process;

p12:process(cnt2b2)
    begin
   if WR = '0' THEN
       case cnt2b2 is

       when 0 => DATA(MSPDATA-1 downto 0)<=DATAOUT(DSIZE-1 downto 24);
       when 1 => DATA(MSPDATA-1 downto 0)<=DATAOUT(23 downto 16);
       when 2 => DATA(MSPDATA-1 downto 0)<=DATAOUT(15 downto 8);
       when 3 => DATA(MSPDATA-1 downto 0)<=DATAOUT(7 downto 0);
       when others => DATA(MSPDATA-1 downto 0)<="11111111";
     end case;
     end if;
 end process;

end architecture behavioral;