config_s.v

来自「一个RAM的测试仿真程序」· Verilog 代码 · 共 191 行

 `timescale 1ps / 1ps
module config_s
	(
		clk,
		rst_n,
		config_CE,
		cmdack,
		addr,
		datain,
		cmd,
		finish_F
		
	);
  
  	input         clk;
	input         rst_n;
	input         config_CE;//高电平此模块有效
	input         cmdack;
	output [2:0]       cmd;
	output [22:0] addr;
	output [15:0] datain; 
	output        finish_F;
	
	
	
	parameter s0 = 0, s1 = 1, s2 = 2, s3 = 3, s4 = 4;
    parameter s5 = 5, s6 = 6, s7 = 7, s8 = 8, s9 = 9, IDLE = 10;
   
	reg [3:0]  state;
	reg [3:0]  next_state;
	
	reg [22:0] addr;
	reg [15:0] datain;
	reg [2:0]  cmd;
	reg[1:0]   dm;
	reg        finish_F;
	
   //---------时序进程-----------------------------------------
	always @ (posedge clk)
		if (!rst_n)
			begin
			state <= IDLE;
			end

		else
			state <= next_state;
	//---------状态转换进程------------------------------------
	always @ (state or cmdack or config_CE)
		case (state)
	//------------s0-s7是初始化sdram程序------------------------
			s0:
			begin
			        datain[15:0] <= 16'bz;
				cmd <= 3'bz;
				addr[22:0]<=23'bz; 
				dm <=4'bz;
				finish_F <= 0;
				next_state <= s1;
			end
			s1 :
			begin
			     addr[22:0]<=23'b0;
				 datain[15:0] <= 16'b0;
			     cmd <= 3'b100;  //issue precharge before issuing load_mode
				 dm <=4'b0000;
				 finish_F <= 0;
              if (cmdack == 1)  // Wait for the controller to ack the command  
                 next_state <= s2;  
              else 
                 next_state <= s1;  
			end
			s2 :
			begin
			    datain[15:0] <= 16'b0;
				cmd <= 3'b000;//nop
				next_state <= s3;
				addr[22:0]<=23'b0; 
				dm <=4'b0000;
				finish_F <= 0;
			end
			s3 :
			begin
			    cmd <= 3'b101;//load_mode
				datain[15:0] <= 16'b0;
			    addr[22:0] <= 23'b0110000 ;     
				dm <=4'b0000;
				finish_F <= 0;
			 	if (cmdack == 1)  // Wait for the controller to ack the command  
                	next_state <= s4;
             	else 
                	next_state <= s3;
			end
			s4 :
			begin
			    addr[22:0]<=23'b0;
				datain[15:0] <= 16'b0;
				cmd <= 3'b000;//nop
				dm <=4'b0000;
				next_state <= s5;
				finish_F <= 0;
				
			end
			s5:
			begin
			     datain[15:0] <= 16'b0;
			     cmd <= 3'b111;  //load_reg2  :确定刷新周期
			     addr[22:0]<=23'b010111110110;  
				 dm <=4'b0000;
				 finish_F <= 0;
              if (cmdack == 1)  // Wait for the controller to ack the command  
                 next_state <= s6;  
              else 
                 next_state <= s5;  
			end
			
			s6 :
			begin
			    addr[22:0]<=23'b0;
				datain[15:0] <= 16'b0;
				cmd <= 3'b000;//nop
				dm <=4'b0000;
				next_state <= s7;
				finish_F <= 0;
			
			end
			
			s7:
			 begin
			     datain[15:0] <= 16'b0;
			     cmd <= 3'b110;  //load_reg1  :确定控制方式
			     addr[22:0]<=23'b000000001111;  //单纯读写一个字节。自动预充电。
				 dm <=4'b0000;
				 finish_F <= 0;
              if (cmdack == 1)  // Wait for the controller to ack the command  
                 next_state <= s8;  
              else 
                 next_state <= s7;  
			end	
			
			s8 :
			begin
			    addr[22:0]<=23'b0;
				datain[15:0] <= 16'b0;
				cmd <= 3'b000;//nop
				dm <=4'b0000;
				next_state <= s9;   
                                finish_F <=1;
			end
			s9:
			begin
			   addr[22:0]<=23'bz;
			   datain[15:0] <= 16'bz;
			   cmd <= 3'bz;
			   dm <=4'bz;
			   next_state <= IDLE;
			   finish_F <= 1;//连续2个周期为1。避免主程序检测不到。
			end
			IDLE:
			begin
		    	if (config_CE == 1)
					begin
			    	next_state <= s0;
					finish_F <= 0;
					cmd <= 3'bz;
					addr[22:0]<=23'bz;
					datain[15:0] <= 16'bz;
					end
				else
					begin
		   				addr[22:0]<=23'bz;
						datain[15:0] <= 16'bz;
						cmd <= 3'bz;//nop
						dm <=4'bz;
						next_state <= IDLE;
						finish_F <= 0;
					end
			end
			 	
			default: 
				begin 
				addr[22:0]<=23'bz;
				datain[15:0] <= 16'bz;
				cmd <= 3'bz;//nop
				dm <=4'bz;
				next_state <= IDLE;
				finish_F <= 0;
				end
		endcase

endmodule