代码搜索：dataIn
找到约 2,888 项符合「dataIn」的源代码
代码结果 2,888
www.eeworm.com/read/302514/13833400
v map_lpm_ram.v
module map_lpm_ram(dataout,datain,addr,we,inclk,outclk);
input[15:0] datain;
input[7:0] addr;
input we,inclk,outclk;
output[15:0] dataout;
lpm_ram_dq ram(.data(datain),.address(addr),.we(we),.i
www.eeworm.com/read/252441/6298427
v map_lpm_ram.v
module map_lpm_ram(dataout,datain,addr,we,inclk,outclk);
input[15:0] datain;
input[7:0] addr;
input we,inclk,outclk;
output[15:0] dataout;
lpm_ram_dq ram(.data(datain),.address(addr),.we(we),.i
www.eeworm.com/read/478119/6358293
vhd disctrl.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DISCTRL IS
PORT(
CLK : IN STD_LOGIC;
DATAIN : IN STD_LOGIC_VECTOR(11 do
www.eeworm.com/read/491340/6438810
v map_lpm_ram.v
module map_lpm_ram(dataout,datain,addr,we,inclk,outclk);
input[15:0] datain;
input[7:0] addr;
input we,inclk,outclk;
output[15:0] dataout;
lpm_ram_dq ram(.data(datain),.address(addr),.we(we),.i
www.eeworm.com/read/490387/6455689
vhd ledmux.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ledmux IS
PORT(
datain :IN STD_LOGIC_VECTOR(29 DOWNTO 0);
ledaddr :IN STD_LOGIC_VECTOR(2 DOWNTO 0);
dataout :OUT STD_LOGIC_VECTOR
www.eeworm.com/read/488704/6484314
hier_info char_7seg.hier_info
|char_7seg
SW[1] => Mux1.IN5
SW[1] => Mux0.IN5
SW[1] => hex00[1].DATAIN
SW[1] => hex00[2].DATAIN
SW[0] => Mux1.IN4
SW[0] => Mux0.IN4
SW[0] => hex00[3].DATAIN
SW[0] => hex00[4].DATAIN
SW[0] =>
www.eeworm.com/read/483608/6599536
v map_lpm_ram.v
module map_lpm_ram(dataout,datain,addr,we,inclk,outclk);
input[15:0] datain;
input[7:0] addr;
input we,inclk,outclk;
output[15:0] dataout;
lpm_ram_dq ram(.data(datain),.address(addr),.we(we),.i
www.eeworm.com/read/481648/6636810
v map_lpm_ram.v
module map_lpm_ram(dataout,datain,addr,we,inclk,outclk);
input[15:0] datain;
input[7:0] addr;
input we,inclk,outclk;
output[15:0] dataout;
lpm_ram_dq ram(.data(datain),.address(addr),.we(we),.i
www.eeworm.com/read/480128/6677394
vhd shift_reg.vhd
library ieee;
use ieee.std_logic_1164.all;
entity shift_reg is
generic( dlzka : natural :=7);
port(
datain : in std_logic;
clk : in std_logic;
rst : in std_logic;
ss : in std_logic;
www.eeworm.com/read/479927/6683642
v map_lpm_ram.v
module map_lpm_ram(dataout,datain,addr,we,inclk,outclk);
input[15:0] datain;
input[7:0] addr;
input we,inclk,outclk;
output[15:0] dataout;
lpm_ram_dq ram(.data(datain),.address(addr),.we(we),.i