disctrl.vhd

来自「设计了一个计数范围是0到99的BCD计数器并可以显示出来的」· VHDL 代码 · 共 44 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DISCTRL IS
  PORT(
		CLK	 : IN	STD_LOGIC;
		DATAIN	 : IN 	STD_LOGIC_VECTOR(11 downto 0);
		SEG : OUT	STD_LOGIC_VECTOR(6 downto 0);
        SEL  : OUT	STD_LOGIC_VECTOR(7 downto 0)
      );
END DISCTRL;

ARCHITECTURE ART OF DISCTRL IS
SIGNAL CHOICE :   STD_LOGIC_VECTOR(2 downto 0);
SIGNAL DATAOUT :  STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
 PROCESS (CLK)
 BEGIN
   IF CLK'EVENT AND CLK='1' THEN
     CHOICE<=CHOICE+1;
   END IF;
 END PROCESS;
 SEL <= "00000001" WHEN CHOICE=0 ELSE
		"00000010" WHEN CHOICE=1 ELSE
		"00000100" WHEN CHOICE=2 ELSE
        "00000000";
 DATAOUT <= DATAIN(3 DOWNTO 0) WHEN CHOICE=0 ELSE
		    DATAIN(7 DOWNTO 4) WHEN CHOICE=1 ELSE
		    DATAIN(11 DOWNTO 8);
 WITH DATAOUT SELECT
      SEG  <= "1111110" WHEN "0000",
			  "0110000" WHEN "0001",
			  "1101101" WHEN "0010",
			  "1111001" WHEN "0011",
			  "0110011" WHEN "0100",
			  "1011011" WHEN "0101",
			  "1011111" WHEN "0110",
			  "1110000" WHEN "0111",
			  "1111111" WHEN "1000",
			  "1111011" WHEN OTHERS;
END ART;