counter10.vhd

来自「设计了一个计数范围是0到99的BCD计数器并可以显示出来的」· VHDL 代码 · 共 38 行

--******************************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--******************************************************
ENTITY COUNTER10 IS
	PORT(
			CLK	     :  IN  STD_LOGIC;		
			CLR      :  IN  STD_LOGIC;				
			ENA      :  IN  STD_LOGIC;
            CY10     :  OUT STD_LOGIC;
            SUM      :  OUT STD_LOGIC_VECTOR(3 DOWNTO 0)				
		);
END COUNTER10;
--*******************************************************
ARCHITECTURE ART OF COUNTER10 IS
    SIGNAL Q  : STD_LOGIC_VECTOR(3 DOWNTO 0);
    SIGNAL RST,DLY:STD_LOGIC;
	BEGIN
    PROCESS (CLK,RST)
	BEGIN
	    IF RST='1' THEN
			Q<= "0000";
		ELSIF CLK'EVENT AND CLK = '1' THEN
			DLY <= Q(3);
			IF ENA = '1' THEN
				Q <= Q+1;
			END IF; 			
		END IF;
	END PROCESS;
	CY10<= NOT Q(3) AND DLY;
	RST <= '1' WHEN Q=10 OR CLR='1' ELSE
		   '0';
	SUM <= Q;
END ART;