shift_reg.vhd

Simple shift register with testbench in vhdl

library ieee;
use ieee.std_logic_1164.all;

entity shift_reg is
generic( dlzka : natural :=7);
port(
	datain	: in std_logic;
	clk		: in std_logic;
	rst		: in std_logic;
	ss		: in std_logic;
	dataout	: out std_logic);
end shift_reg;

architecture arch of shift_reg is

	signal shiftin	: std_logic_vector(dlzka downto 0):="00000000";
begin
		
	process(clk)
	begin
		if rst='1' then
			shiftin<=(others=>'0');
		elsif rising_edge(clk) then
			if ss='0' then
				shiftin<=datain & shiftin(dlzka downto 1);
			end if;
		end if;
	end process;
	dataout<=shiftin(0);
end arch;