tb.vhd

来自「Simple shift register with testbench in 」· VHDL 代码 · 共 64 行

library ieee;
use ieee.std_logic_1164.all;

entity tb is
end tb;

architecture arch of tb is
	component shift_reg
	port(
		datain	: in std_logic;
		clk		: in std_logic;
		rst		: in std_logic;
		ss		: in std_logic;
		dataout	: out std_logic);
	end component;

	signal tb_datain	: std_logic;
	signal tb_clk	: std_logic;
	signal tb_ss	: std_logic;
	signal tb_dataout: std_logic;
	signal tb_rst	: std_logic;

begin
	tb_shift_reg: shift_reg
		port map(
			datain=>tb_datain,
			clk=>tb_clk,
			ss=>tb_ss,
			rst=>tb_rst,
			dataout=>tb_dataout);

	clock:process
	begin
		tb_clk<='0';
		wait for 5ns;
		tb_clk<='1';
		wait for 5ns;
	end process;
	
	tb_rst<='0';

	stimuli:process
	begin
		tb_ss<='0';
		tb_datain<='0';
		wait for 20ns;
		tb_datain<='1';
		wait for 10ns;
		tb_datain<='1';
		wait for 10ns;
		tb_datain<='0';
		wait for 10ns;
		tb_datain<='0';
		wait for 10ns;
		tb_datain<='1';
		wait for 10ns;
		tb_datain<='0';
		wait for 10ns;
		tb_datain<='1';
		wait for 10ns;
		tb_datain<='0';
	    wait;
	end process;
end arch;