代码搜索：dataIn
找到约 2,888 项符合「dataIn」的源代码
代码结果 2,888
www.eeworm.com/read/307931/13713085
v eth_register.v
`include "timescale.v"
module eth_register(DataIn, DataOut, Write, Clk, Reset, SyncReset);
parameter WIDTH = 8; // default parameter of the register width
parameter RESET_VALUE = 0;
in
www.eeworm.com/read/307606/13719521
vhd calc.vhd
--------------------------------------------------------------------------------------------------------------------
--实验题号 : Ex4-1
--项目名称 : 计算器
--文件名 : Calc.vhd
--作者 : 田甲
--班号.
www.eeworm.com/read/307265/13724942
txt 6.3.5快速排序.txt
DATS EQU 20H
N EQU 5DH
QUEUE EQU 1FH
F DATA 3CH
R DATA 3DH
TST:
MOV DPTR,#LIST
MOV P2,#DATS
MOV R0,#0
MOV R2,#N
CPY:
CLR A
MOVC A,@A+DPTR
MOVX @R0,A
INC DPTR
www.eeworm.com/read/305180/13777429
wsf wed.wsf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
www.eeworm.com/read/303278/13819214
txt 6.3.5快速排序.txt
DATS EQU 20H
N EQU 5DH
QUEUE EQU 1FH
F DATA 3CH
R DATA 3DH
TST:
MOV DPTR,#LIST
MOV P2,#DATS
MOV R0,#0
MOV R2,#N
CPY:
CLR A
MOVC A,@A+DPTR
MOVX @R0,A
INC DPTR
www.eeworm.com/read/453490/6311037
v sdr_data_path.v
module sdr_data_path(
CLK,
RESET_N,
DATAIN,
DM,
DQOUT,
DQM
);
`include "Sdram_Params.h"
input CLK;
www.eeworm.com/read/491204/6441688
vhd ad.vhd
--AD
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity ad is
port(busy:in std_logic;
datain:in unsigned(7 downto 0);
clk:in std_logic;
dataout:out un
www.eeworm.com/read/491205/6441742
vhd ad.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity ad is
port(busy:in std_logic;
datain:in unsigned(7 downto 0);
clk:in std_logic;
dataout:out unsigned
www.eeworm.com/read/489800/6461495
vhd mealy.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY mealy IS
PORT(clk,datain,reset : IN STD_LOGIC;
q : out STD_LOGIC_vector(4 downto 0));
END mealy;
ARCHITECTURE a OF meal
www.eeworm.com/read/487822/6500725
v sdr_data_path.v
module sdr_data_path(
CLK,
RESET_N,
DATAIN,
DM,
DQOUT,
DQM
);
`include "Sdram_Params.h"
input CLK;