mealy.vhd

计数器、频率计、优先编码器、数码管扫描电路、数据选择器

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY mealy IS
	
	PORT(clk,datain,reset	: IN	STD_LOGIC;
		               q	: out	STD_LOGIC_vector(4 downto 0));
END mealy;
ARCHITECTURE a OF mealy IS	
	type states is (st0,st1,st2,st3,st4);
	signal current_state,next_state : states;
BEGIN
REG:process(reset,clk)
  begin
	if reset='1' then current_state<=st0;
		elsif clk'event and clk='1' then
			current_state<=next_state;
	end if;
end process;	

COM:process(current_state,datain)
  begin
	case current_state is
		when st0 =>
			if datain='0' then q<="01010";
				elsif datain='1' then q<="10000";next_state<=st1;
			end if;
		when st1 =>
			if datain='1' then q<="10100";next_state<=st0;
				elsif datain='0' then q<="10101"; next_state<=st2;
			end if;
		when st2 => 
			if datain='0' then q<="10011"; next_state<=st0;
				elsif datain='1' then q<="10101"; next_state<=st3;
			end if;
		when st3 =>
			if datain='1' then q<="01001"; next_state<=st0;
				elsif datain='0' then q<="11011"; next_state<=st4;
			end if;
		when st4 => next_state<=st0;
			if datain='0' then q<="01101";
				elsif datain='1' then q<="11101";
					end if;					
		when others => null;
	end case;
 end process;
end a;