ad.vhd

来自「硬件电子琴系统设计」· VHDL 代码 · 共 41 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity ad is
port(busy:in std_logic;
 	 datain:in unsigned(7 downto 0);
     clk:in std_logic;
 	 dataout:out unsigned(7 downto 0);
	 cs:out std_logic;
	 rd:out std_logic
 	);
end ad;

architecture behav of ad is
begin
process(clk)
variable count:unsigned(1 downto 0);
begin
if clk'event and clk='1' then
   case count is
      when "00" =>
          cs<='1';
          rd<='1';
          dataout<=datain;
      when "01" =>
          cs<='0';
          rd<='0';
      when "11" =>
          if busy='0' then 
            count:=count-1;
          end if;
      when others =>
          null;
    end case;
count:=count+1;
end if;
end process;
end behav;