calc.vhd

用VHDL写的一个小游戏

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--实验题号   : Ex4-1
--项目名称   : 计算器
--文件名     : Calc.vhd
--作者       : 田甲
--班号.      : 计45 
--创建日期   : 2006-04-20
--目标芯片   : EP1C6Q240C8
--电路模式   : 模式0
--功能描述   : 本文件给出了计算器的结构描述
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LIBRARY IEEE;  
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Calc IS
PORT ( clk , enable , reset: IN STD_LOGIC; 
		datain: IN STD_LOGIC_VECTOR(3 downto 0); 
         Q : OUT STD_LOGIC_VECTOR(23 DOWNTO 0));
END Calc;
ARCHITECTURE impl OF Calc IS
  TYPE states IS (st0, st1, st2, st3,st4);      
  SIGNAL STX : states ; 
  signal va, vb, opout: std_logic_vector(3 downto 0); 
  signal tempQ: std_logic_vector(23 downto 0); 
  signal op: std_logic;
  signal tempsum: std_logic_vector(7 downto 0);
component SubAdd is
port(SAa, SAb: in std_logic_vector(3 downto 0);
    operator: in std_logic;
    sum: out std_logic_vector(7 downto 0) );
end component;
BEGIN                          
 COMREG : PROCESS(CLK,ENABLE, reset)  BEGIN --决定转换状态的进程
      IF reset='1' THEN    STX <= ST0;
      ELSIF CLK'EVENT AND CLK = '1' THEN    CASE STX IS           
        WHEN st0 => 
			IF ((not datain(3)) or (datain(3) and (not datain(2)) and (not datain(1)))) = '1' and enable = '1' THEN  
				STX <= st1; 
				va <= datain;
			else va <= "1111";
			END IF;
        WHEN st1 => 
		IF DATAIN = "1010" and enable = '1'	THEN  
			STX <= st2;
			op <= '0';
			opout <= "1010";
		elsif DATAIN = "1011" and enable = '1' then
			STX <= st2;
			op <= '1';
			opout <= "1011";
		elsif ((not datain(3)) or (datain(3) and (not datain(2)) and (not datain(1)))) = '1' and enable = '1' then
			va <= datain;
		else
			opout <= "1111";
     	END IF;
        WHEN st2 => 			
			IF ((not datain(3)) or (datain(3) and (not datain(2)) and (not datain(1)))) = '1' and enable = '1' THEN  
				STX <= st3; 
				vb <= datain;
			elsif datain = "1010" and enable = '1' then
				op <= '0';
				opout <= "1010";
			elsif datain = "1011" and enable = '1' then
				op <= '1';
				opout <= "1011";
			else 
				vb <= "1111";
			END IF;
        WHEN st3 => 
			IF DATAIN = "1100" and enable = '1'	THEN  
				STX <= st4; 
			elsif ((not datain(3)) or (datain(3) and (not datain(2)) and (not datain(1)))) = '1' and enable = '1' then
				vb <= datain;
			END IF;
        WHEN st4 => 
			IF DATAIN = "1101" and enable = '1' THEN  STX <= st0; END IF;
        WHEN OTHERS => STX <= st0; 
     END CASE ;
   END IF;
 END PROCESS COMREG ;
  u1: SubAdd port map
    (SAa=>va, SAb=>vb, operator=>op, sum=>tempsum); 
COM1: PROCESS(STX, va, opout, vb, tempsum) BEGIN --输出控制信号的进程
   CASE STX IS           
    WHEN st0 => tempQ(23 downto 0) <= "111111111111111111111111";
    WHEN st1 => tempQ(19 downto 0) <= "11111111111111111111"; tempQ(23 downto 20) <= va;                  
    WHEN st2 => tempQ(15 downto 0) <= "1111111111111111"; 
		 tempQ(23 downto 20) <= va; tempQ(19 downto 16) <= opout;
    WHEN st3=>  tempQ(11 downto 0) <= "111111111111"; 
		 tempQ(23 downto 20) <= va; tempQ(19 downto 16) <= opout; tempQ(15 downto 12) <= vb;
    WHEN st4=>  tempQ(23 downto 20) <= va; tempQ(19 downto 16) <= opout; tempQ(15 downto 12) <= vb; tempQ(11 downto 8) <= "1100";
		 tempQ(7 downto 0) <= tempsum;                           
    WHEN OTHERS =>  tempQ<="111111111111111111111111" ;                
  END CASE ;
  END PROCESS COM1 ;
  Q <= tempQ;
END impl;