代码搜索：controlunit
找到约 106 项符合「controlunit」的源代码
代码结果 106
www.eeworm.com/read/300195/13929547
hif controlunit.hif
Version 5.1 Build 176 10/26/2005 SJ Full Version
37
1903
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
# entity
lpm_rom
# storage
www.eeworm.com/read/300195/13929614
mif controlunit.mif
-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any o
www.eeworm.com/read/300195/13929616
vhd controlunit.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE ram_constants IS
constant DATA_WIDTH : INTEGER := 8;
constant ADDR_WIDTH : INTEGER := 8;
END ram_const
www.eeworm.com/read/300195/13929629
pin controlunit.pin
-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and a
www.eeworm.com/read/199424/7860714
vhd v_controlunit.vhd
----------------------------------------------------------------------------
---- ----
---- WISHBONE RISCMCU IP Core ----
---- ----
---- This file is part of the RISCMCU projec
www.eeworm.com/read/306761/13738099
bak controlunit.vhd.bak
-- cu.vhdl
--
-- Control unit
--
library ieee;
use ieee.std_logic_1164.all;
use work.mips_pack.all;
entity cu is
port (instr_in: in std_ulogic_vector(31 downto 0);
pc_next: in std_ulogic_v
www.eeworm.com/read/480253/6668646
vhd v_controlunit.vhd
----------------------------------------------------------------------------
---- ----
---- WISHBONE RISCMCU IP Core ----
---- ----
---- This file is part of the RISCMCU projec
www.eeworm.com/read/409536/11320245
vhd v_controlunit.vhd
----------------------------------------------------------------------------
---- ----
---- WISHBONE RISCMCU IP Core ----
---- ----
---- This file is part of the RISCMCU pr
www.eeworm.com/read/346349/11753783
vhd v_controlunit.vhd
----------------------------------------------------------------------------
---- ----
---- WISHBONE RISCMCU IP Core ----
---- ----
---- This file is part of the RISCMCU projec
www.eeworm.com/read/126357/14427760
bak controlunit.v.bak
//controlunit.v
//global sequencial control
module controlunit(rd1_en, rd2_en, wt3_en, pc_en, alu_en, de_en, ir_wt, a_in, b_in, dr_wt,
dmrd_en, dmwt_en, imrd_en, clk, rst, op_in);
input clk