controlunit.v.bak

用verilog编写在FLEX10K上实现的简易CPU

//controlunit.v
//global sequencial control 

module controlunit(rd1_en, rd2_en, wt3_en, pc_en, alu_en, de_en, ir_wt, a_in, b_in, dr_wt,
				   dmrd_en, dmwt_en, imrd_en, clk, rst, op_in);
	input 	clk, rst, op_in/*the type of inst. delivered by decoder*/;
	
	output 	ir_wt, 	//load instruction from 
			a_in, b_in, //alu operand 
			dr_wt,	//write to dr
			rd1_en, rd2_en, wt3_en, //register file accession enable
			pc_en, 	//enable pc to be changed , add or jmp
			alu_en, //allow alu to compute
			de_en,  //decode instruction
			dmrd_en, //enable data memory to be read
			dmwt_en, //enable data memory to be writen
			imrd_en; //enable instruction memory to be read
			
	reg 	ir_wt, dr_wt, rd1_en, rd2_en, wt3_en, pc_en, a_in, b_in, alu_en, de_en, 
			dmrd_en, dmwt_en, imrd_en, imwt_en;
			
	wire[1:0]	op_in;	
	reg[1:0] op_type;	
	
	//state machine
	reg[3:0]	ctrl_state;
	parameter 	ins_ftch = 	4'h0,	//instruction fetch, access the instruction memory
				ins_de =	4'h1,	//instruction decode 
				addr_cmpt = 4'h2,	//data memory address computation
				jmp_cmpt = 	4'h3,	//branch address computaton
				alu_exe =	4'h4,	//alu and shift executation
				jmp = 		4'h5,	//jump 
				rd_dm = 	4'h6,	//read data form memory, for loading 
				wt_dm = 	4'h7,	//write data to memory, for storing
				wt_bck =	4'h8;	//write back to register file , for loading
			
	always@(posedge clk)		
	begin
		if(rst)
		begin
			ir_wt <= 0;
			a_in <= 0;
			b_in <= 0; 
			dr_wt <= 0;
			
			rd1_en <= 0; 
			rd2_en <= 0;
			wt3_en <= 0;
			pc_en <= 0;
			
			alu_en <= 0;
			de_en <= 0;
			dmrd_en <= 0;
			dmwt_en <= 0;
			
			imrd_en <= 0;
			ctrl_state <= 4'h0;
		end
		else
			case(ctrl_state)
			ins_ftch:	
			begin
				ir_wt <= 1;
				a_in <= 0;
				b_in <= 0; 
				dr_wt <= 0;
				
				rd1_en <= 0; 
				rd2_en <= 0;
				wt3_en <= 0;
				pc_en <= 0;
				
				alu_en <= 0;
				de_en <= 1;
				dmrd_en <= 0;
				dmwt_en <= 0;
				
				imrd_en <= 1;		//read inst. from instr. memo.
				//prepare for next step
			   op_type <= op_in;	//get the operation type: alu, jmp, store or load ?
				ctrl_state <= ins_de;	
			end
			ins_de:
			begin
				dr_wt <= 0;
				wt3_en <= 0;
				alu_en <= 0;
				dmrd_en <= 0;
				dmwt_en <= 0;
				imrd_en <= 1;
				
				ir_wt <= 1;			//read instr. register
				de_en <= 1;			//decode instruction
				pc_en <= 1;			//computer the next instr. addr.
				rd1_en <= 1;			//read from the register file 
				
				rd2_en <= 1;			//	
				a_in   <= 1;			//get the operand from register
				b_in   <= 1;			//
				//prepare for next step
				op_type <= op_in;	//get the operation type: alu, jmp, store or load ?
				ctrl_state <= alu_exe;
			end
			alu_exe:
			begin
				ir_wt <= 0;
				a_in <= 0;
				b_in <= 0; 
				dr_wt <= 0;
				   
				rd1_en <= 0; 
				rd2_en <= 0;
				wt3_en <= 0;
				pc_en <= 0;
				
				de_en <= 0;
				dmrd_en <= 0;
				dmwt_en <= 0;
				imrd_en <= 0;
				
				alu_en <= 1;			//enable alu to compute
				//prepare for next step
				op_type <= op_in;	//get the operation type: alu, jmp, store or load ?
				//ctrl_state <= wt_bck;
				case(op_in[1:0])		
					2'b00:	ctrl_state <= wt_bck;		//ALU and SHIFT
					2'b01:	ctrl_state <= wt_bck;							//JMP
					2'b10:	ctrl_state <= wt_dm;		//STORE
					2'b11:	ctrl_state <= rd_dm;		//LOAD
				endcase
				
			end
			rd_dm:
			begin		
				ir_wt <= 0;
				a_in <= 0;
				b_in <= 0; 
				rd1_en <= 0; 
				
				rd2_en <= 0;
				wt3_en <= 0;
				pc_en <= 0;
				alu_en <= 0;
				
				de_en <= 0;
				dmrd_en <= 0;
				imrd_en <= 0;
				
				dr_wt <= 1;				//read from the dm
				dmrd_en <= 1;			//	to dr	
				ctrl_state <= wt_bck;	//move data from memo. to register file
			end
			wt_dm:
			begin
				ir_wt <= 0;
				a_in <= 0;
				b_in <= 0; 
				dr_wt <= 0;
				rd1_en <= 0; 
				rd2_en <= 0;
				wt3_en <= 0;
				pc_en <= 0;
				de_en <= 0;
				dmrd_en <= 0;
				dmwt_en <= 0;
				imrd_en <= 0;
				alu_en <= 0;			
							
				dmwt_en <= 1;			//write to the dm
				ctrl_state <= ins_ftch;			
			end
			wt_bck:
			begin
				ir_wt <= 0;
				a_in <= 0;
				b_in <= 0; 
				rd1_en <= 0; 
				rd2_en <= 0;
				wt3_en <= 0;
				pc_en <= 0;
				de_en <= 0;
				dmrd_en <= 0;
				dmwt_en <= 0;
				imrd_en <= 0;
				
				dr_wt <= 1;
				alu_en <= 1;			//enable alu to compute			
				wt3_en <= 1;			//write back from alu or dm
				ctrl_state <= ins_ftch;
			end
		endcase
	end
			
endmodule