controlunit.vhd

CPU设计中的controlunit源码

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;


PACKAGE ram_constants IS
  constant DATA_WIDTH : INTEGER := 8;
  constant ADDR_WIDTH : INTEGER := 8;
END ram_constants; 

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY lpm;
USE lpm.lpm_components.ALL;
LIBRARY work;
USE work.ram_constants.ALL;





entity controlunit is
port(
clk:in std_logic;
flag:in std_logic_vector(7 downto 0);            --to determine what is the next action
IR: in std_logic_vector(7 downto 0);     --input to mar register
control_signal:out std_logic_vector(7 downto 0)  --control signals output
);

end controlunit;



architecture structual of controlunit is
signal CAR:std_logic_vector(7 downto 0);
signal CBR:std_logic_vector(7 downto 0);
signal we:std_logic;
signal temp:std_logic_vector(7 downto 0);
signal decode_ir:integer;
--这里把squencing logic写成一个函数
function decode(instruction:std_logic_vector(7 downto 0))  return  integer is
variable IR_decode:integer;
begin
case instruction is
when "00000010"  => IR_decode:=1 ;   --store;
when "00000001"  => IR_decode:=2;   --load;
when "00000011"  => IR_decode:=3;   --ADD
when "00000100"  => IR_decode:=4;   --sub
when "00000101"  => IR_decode:=5;   --JMPGEZ
when "00000110"  => IR_decode:=6;   --JMP
when "00000111"  => IR_decode:=14;   --halt
when "00001010"  => IR_decode:=7;   --and
when "00001011"  => IR_decode:=8;   --or
when "00001100"  => IR_decode:=9;   --not 
when "00001101"  => IR_decode:=10;   --SRR
when "00001110"  => IR_decode:=11;  --SRL
when "00001000"  => IR_decode:=12;   --MPY
when "00001001"  => IR_decode:=13;   --DIV
when others => IR_decode:=14;
end case;
return (IR_decode); 
end decode;






begin 

U5: lpm_rom
GENERIC MAP (
 lpm_widthad => ADDR_WIDTH,
 lpm_outdata => "UNREGISTERED",
 --lpm_indata => "UNREGISTERED",
 --lpm_address_control => "UNREGISTERED",
 lpm_file => "controlunit.mif",-- fill ram with content of file program.mif
 lpm_width => DATA_WIDTH )
 PORT MAP (
 address => CAR,
 inclock=>clk,
 memenab => we, 
 q=>CBR);




Squencing_logic: process(clk,flag) 
BEGIN
if(clk'event and clk='1') then 
we<='0';
--decode_ir<=decode(IR);
case CBR is
when "00000011" =>
    case decode(IR) is
           when  1 =>  CAR<="00000011";we<='1';  --store
           when  2 =>  CAR<="00000111";we<='1';  --load
           when  3 =>  CAR<="00001011";we<='1';  --ADD
           when  4 =>  CAR<="00010001";we<='1';  --sub
           when  5 =>  CAR<="00010110";we<='1';  --JMPGEZ  
           when  6 =>  CAR<="00011110";we<='1';  --JMP
           when  7 =>  CAR<="00100010";we<='1';  --and
           when  8 =>  CAR<="00100111";we<='1';  --or
           when  9 =>  CAR<="00101011";we<='1';  --not
           when  10 => CAR<="00110010";we<='1';  --srr
           when  11 => CAR<="00110100";we<='1';  --srl  
           when  12 => CAR<="00110110";we<='1';  --mpy
           when  13 => CAR<="00111010";we<='1';  --div
           when  14 => CAR<="00000111";we<='1';  --halt
           when others =>NULL;
   end case;

when "00001010" =>  CAR<="00000000";we<='1';

when "00001111" =>  we<='1';
if(flag(7)='1') then  
if(flag(4)='1') then --溢出
     CAR<="00010000";
 else CAR<="00010001"; end if;
else temp<=CBR;
      CAR<="01000000";
end if;


--以下的操作与ACC有关，必须等到ACC完成标志为1后才能执行下一步的操作
when "00010101" | "00010110"  |"00010111"| "00011000" | "00011001" | "00011010" |"00011011"
 =>         
we<='1'; CAR<=CAR + "00000001";

when "01000000"=>
if(flag(7)='1') then  CAR<=temp;
end if;



when others =>we<='1'; CAR<=CAR+"00000001";
end case;

we<='1';control_signal<=CBR;

end if;
end process Squencing_logic;




end  structual;